Abstract: A stylus system and method for determining the three-dimensional position and orientation of a stylus operating within a volume located above a surface of a display device is described. In some embodiments, the stylus system includes a stylus and a display device. The stylus senses one or more magnetic fields generated from a set of transmitting coils associated with the display device and transmits sensing information over an RF channel to a receiver in the display device. The display device determines the three-dimensional position of the stylus by applying a cell-based position reconstruction technique that compares the received sensing information with predetermined magnetic field values associated with one or more predetermined regions located above the surface of the display device. The cell-based position reconstruction technique accommodates magnetic field distortions due to the presence of conductive elements within or near the display device.

Abstract: A system and method for operating a light emitting device utilizing charged quantum dots is described. In one embodiment, charged quantum dots are suspended in a liquid between an excitation plate and a cover plate. The excitation plate carries short-wave excitation light. Charged quantum dots near the surface of the excitation plate may emit light in response to an evanescent field generated by the short-wave excitation light undergoing total internal reflection within the excitation plate. The excitation plate and the cover plate may be coated with one or more transparent electrodes. The movement of charged quantum dots within the liquid may be controlled by applying one or more bias voltages to the one or more transparent electrodes. Light emission from a particular region near the surface of the excitation plate may be controlled by moving charged quantum dots into or out of the particular region.

Abstract: A local user of a local mobile device is allowed to participate in a video conference session with a remote user of a remote mobile device. Live video can be shared between and collaboratively digitally annotated by the local and remote users. An application can also be shared between and collaboratively digitally annotated by the local and remote users. A digital object can also be shared between and collaboratively digitally annotated by the local and remote users.

Abstract: A stylus device receives light from a display though an optical element that is adapted to increase the field curvature of an image formed on an image sensor of the stylus device. Based on the size and shape of a portion of the image that is in focus, a distance, orientation, and/or azimuth of the stylus device with respect to the display can be determined. In addition, a position corresponding to each pixel, or groups of pixels, is encoded into blue light emitted by each pixel or group of pixels of the display. Upon initialization, or after a loss of synchronization, the stylus device can determine its position with respect to the pixels by decoding the encoded position. After synchronizing its position with the display, the stylus device can determine its subsequent positions by tracking pixels of the display.

Abstract: The non-negative single-source shortest path (NSSP) problem is solved on a graph by using a preprocessing phase and then, in a query phase, computing the distances from a given source in the graph with a linear sweep over all the vertices. Contraction hierarchies may be used in the preprocessing phase and in the query phase. Optimizations may include reordering the vertices in advance to exploit locality, performing multiple NSSP computations simultaneously, marking vertices during initialization, and using parallelism. Techniques may be performed on a graphics processing unit (GPU). This makes applications based on all-pairs shortest-paths practical for continental-sized road networks. The applications include, for example, computing graph diameter, exact arc flags, and centrality measures such as exact reaches or betweenness.

Abstract: A system and method for operating a light emitting device utilizing charged quantum dots is described. In one embodiment, charged quantum dots are suspended in a liquid between an excitation plate and a cover plate. The excitation plate carries short-wave excitation light. Charged quantum dots near the surface of the excitation plate may emit light in response to an evanescent field generated by the short-wave excitation light undergoing total internal reflection within the excitation plate. The excitation plate and the cover plate may be coated with one or more transparent electrodes. The movement of charged quantum dots within the liquid may be controlled by applying one or more bias voltages to the one or more transparent electrodes. Light emission from a particular region near the surface of the excitation plate may be controlled by moving charged quantum dots into or out of the particular region.

Abstract: A stylus system and method for determining the three-dimensional position and orientation of a stylus operating within a volume located above a surface of a display device is described. In some embodiments, the stylus system includes a stylus and a display device. The stylus senses one or more magnetic fields generated from a set of transmitting coils associated with the display device and transmits sensing information over an RF channel to a receiver in the display device. The display device determines the three-dimensional position of the stylus by applying a cell-based position reconstruction technique that compares the received sensing information with predetermined magnetic field values associated with one or more predetermined regions located above the surface of the display device. The cell-based position reconstruction technique accommodates magnetic field distortions due to the presence of conductive elements within or near the display device.

Abstract: A stylus device receives light from a display though an optical element that is adapted to increase the field curvature of an image formed on an image sensor of the stylus device. Based on the size and shape of a portion of the image that is in focus, a distance, orientation, and/or azimuth of the stylus device with respect to the display can be determined. In addition, a position corresponding to each pixel, or groups of pixels, is encoded into blue light emitted by each pixel or group of pixels of the display. Upon initialization, or after a loss of synchronization, the stylus device can determine its position with respect to the pixels by decoding the encoded position. After synchronizing its position with the display, the stylus device can determine its subsequent positions by tracking pixels of the display.

Abstract: The non-negative single-source shortest path (NSSP) problem is solved on a graph by using a preprocessing phase and then, in a query phase, computing the distances from a given source in the graph with a linear sweep over all the vertices. Contraction hierarchies may be used in the preprocessing phase and in the query phase. Optimizations may include reordering the vertices in advance to exploit locality, performing multiple NSSP computations simultaneously, marking vertices during initialization, and using parallelism. Techniques may be performed on a graphics processing unit (GPU). This makes applications based on all-pairs shortest-paths practical for continental-sized road networks. The applications include, for example, computing graph diameter, exact arc flags, and centrality measures such as exact reaches or betweenness.

Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.

Abstract: A surround-vision display system with a very high visual dynamic range is made possible by distributing a limited number of LED's on the inside of a drum and then spinning that drum around a user. The pixel information for each horizontal position in space is sent to each corresponding LED it visits that position. The LED's are arranged in a grid on a panel tile, and the panel tile is tilted slightly, e.g., at 1.1-degrees. The result is each panel tile presents a continuous vertical stripe in the picture frame as all its LED's are swept by in the drum motion. Several panel tiles stacked vertically inside the drum all contribute to the whole height of the picture frame, e.g., several feet. The entire inside circumference of the drum is populated with the LED panel tiles to keep frame refresh rates up to avoid flicker while keeping drum rotation speeds down to reasonable levels. Thus even though the LED's and drum are moving, the image projected appears to be relatively stationary.

Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.

Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.

Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.

Abstract: A surround-vision display system with a very high visual dynamic range is made possible by distributing a limited number of LED's on the inside of a drum and then spinning that drum around a user. The pixel information for each horizontal position in space is sent to each corresponding LED it visits that position. The LED's are arranged in a grid on a panel tile, and the panel tile is tilted slightly, e.g., at 1.1-degrees. The result is each panel tile presents a continuous vertical stripe in the picture frame as all its LED's are swept by in the drum motion. Several panel tiles stacked vertically inside the drum all contribute to the whole height of the picture frame, e.g., several feet. The entire inside circumference of the drum is populated with the LED panel tiles to keep frame refresh rates up to avoid flicker while keeping drum rotation speeds down to reasonable levels. Thus even though the LED's and drum are moving, the image projected appears to be relatively stationary.

Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.

Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.

Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.

Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.

Abstract: To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication.