Patents by Inventor Andreas STUECKJUERGEN

Andreas STUECKJUERGEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180233470
    Abstract: A manufacturing method is provided which comprises forming recesses in a front side of a wafer, connecting a first temporary holding body to the front side of the recessed wafer, thereafter thinning the wafer from a back side, connecting a second temporary holding body to the back side, and thereafter removing the first temporary holding body.
    Type: Application
    Filed: February 15, 2018
    Publication date: August 16, 2018
    Applicant: Infineon Technologies AG
    Inventors: Thomas Killer, Markus Brunnbauer, Marina Janker, Adolf Koller, Gabriel Maier, Andreas Mueller-Hipper, Andreas Stueckjuergen, Christine Thoms
  • Publication number: 20160343662
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 24, 2016
    Inventors: Thomas Fischer, Juergen Foerster, Werner Robl, Andreas Stueckjuergen
  • Patent number: 9425146
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Fischer, Juergen Foerster, Werner Robl, Andreas Stueckjuergen
  • Publication number: 20160155680
    Abstract: A semiconductor package includes a semiconductor chip having a first main face and side faces, an encapsulation covering at least the side faces of the semiconductor chip, and an electrical redistribution structure arranged over the first main face of the semiconductor chip. A first main surface of the semiconductor package includes a surface of the electrical redistribution structure and a surface of the encapsulation.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 2, 2016
    Inventors: Andreas Stueckjuergen, Rainer Leuschner, Daniel Porwol
  • Patent number: 8669655
    Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ottmar Geitner, Walter Hartner, Maciej Wojnowski, Ulrich Wachter, Michael Bauer, Andreas Stueckjuergen
  • Publication number: 20140035154
    Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Ottmar Geitner, Walter Hartner, Maciej Wojnowski, Ulrich Wachter, Michael Bauer, Andreas Stueckjuergen
  • Publication number: 20120074572
    Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Inventors: Thomas FISCHER, Juergen FOERSTER, Werner ROBL, Andreas STUECKJUERGEN