Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A number of rank updates of a result matrix to store in an accumulator register having a predetermined size are determined, where the number of rank updates is based on the first precision and the first shape of the first input matrix, the second precision and the second shape of the second input matrix, and the predetermined size of the accumulator register. A plurality of linear algebra operations is repeated in parallel within the compute array to update the result matrix in the accumulator register based on the first input matrix, the second input matrix, and the number of rank updates.

Abstract: Embodiments of the present invention are directed to a new instruction set extension and a method for providing 3D lane predication for matrix operations. In a non-limiting embodiment of the invention, a first input matrix having m rows and k columns and a second input matrix having k rows and n columns are received by a compute array of a processor. A three-dimensional predicate mask having an M-bit row mask, an N-bit column mask, and a K-bit rank mask is generated. A result matrix of up to m rows, up to n columns, and up to k rank updates is determined based on the first input matrix, the second input matrix, and the predicate mask.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Abstract: The invention relates to saRNA targeting a C/EBP? transcript and therapeutic compositions comprising said saRNA. Methods of using the therapeutic compositions are also provided.

Abstract: An example computer-implemented method includes receiving a first value, a second value, a third value, and a fourth value, wherein the first value, the second value, the third value, and the fourth value are 16-bit or smaller precision floating-point numbers. The method further includes multiplying the first value and the second value to generate a first product, wherein the first product is a 32-bit floating-point number. The method further includes multiplying the third value and the fourth value to generate a second product, wherein the second product is a 32-bit floating-point number. The method further includes summing the first product and the second product to generate a summed value, wherein the summed value is a 32-bit floating-point number. The method further includes adding the summed value to an addend value to generate a result value, wherein the addend value and the result value are 32-bit floating-point numbers.

Abstract: Embodiments of the present invention are directed to a new instruction set extension and a method for providing 3D lane predication for matrix operations. In a non-limiting embodiment of the invention, a first input matrix having m rows and k columns and a second input matrix having k rows and n columns are received by a compute array of a processor. A three-dimensional predicate mask having an M-bit row mask, an N-bit column mask, and a K-bit rank mask is generated. A result matrix of up to m rows, up to n columns, and up to k rank updates is determined based on the first input matrix, the second input matrix, and the predicate mask.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A number of rank updates of a result matrix to store in an accumulator register having a predetermined size are determined, where the number of rank updates is based on the first precision and the first shape of the first input matrix, the second precision and the second shape of the second input matrix, and the predetermined size of the accumulator register. A plurality of linear algebra operations is repeated in parallel within the compute array to update the result matrix in the accumulator register based on the first input matrix, the second input matrix, and the number of rank updates.

Abstract: A processor unit for multiply and accumulate (“MAC”) operations is provided. The present invention may include the processor unit having a plurality of MAC units for performing a set of MAC operations. The present invention may include each MAC unit having an execution unit and a one-write one-read (“1W/1R”) register file, where the 1W/1R register file may have at least one accumulator. The present invention may include the execution unit of each MAC unit being configured to perform a subset of MAC operations by computing a product of a set of values received from another register file of the processor unit and adding the computed product to the at least one accumulator. The present invention may include each MAC unit being configured to perform the respective subset of MAC operations in a single clock cycle.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Abstract: An exhaust muffler for an exhaust system of an internal combustion engine includes a muffler housing (12) with an outer shell (14) enclosing a muffler interior (22), through which exhaust gas can flow. An inner shell (54) is arranged in the muffler interior (22) and covers the outer shell (14) in at least some areas on an inner side (52) facing the muffler interior (22).

Abstract: The present disclosure provides apparatuses and methods for bulb detection for a lighting control system. The apparatus includes a lighting control module configured to cause a transmission of a quantity of electrical energy to a lighting circuit of a light fixture electrically connected to the lighting control module. The apparatus includes a detector circuit positioned in the lighting control module. The detector circuit is configured to measure a response of the lighting circuit to the transmission of the quantity of electrical energy. The apparatus also includes a controller in electrical communication with the detector circuit. The controller is specially programmed to correlate the quantity of electrical energy transmitted to the lighting circuit to the response of the lighting circuit. The controller is further programmed to determine the bulb type of a bulb electrically coupled to the lighting circuit of the light fixture.

Abstract: The present invention relates to a polynucleotide comprising a Nuclear factor of activated T-cells (NFAT) binding site sequence and a reverse complement of said NFAT binding site sequence separated by a spacer sequence, to said polynucleotide for use in treating and/or preventing disease, and to viral particles, compositions, and uses related thereto. The present invention further relates to a polynucleotide comprising a Nuclear factor of activated T-cells (NFAT) binding site sequence and a reverse complement of said NFAT binding site sequence for use in treating and/or preventing an NFAT-mediated disease.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: The invention relates to saRNA targeting a C/EBP? transcript and therapeutic compositions comprising said saRNA. Methods of using the therapeutic compositions are also provided.

Abstract: The invention relates to saRNA targeting a C/EBP? transcript and therapeutic compositions comprising said saRNA. Methods of using the therapeutic compositions are also provided.

Abstract: A stacked-plate heat exchanger may include a plurality of stacked plates. The plurality of stacked plates may include a plurality of first stacked plates and a plurality of second stacked plates stacked alternately one on top of another. Pairs of adjacent stacked plates may each delimit one of a first cavity for the passage of a first fluid and a second cavity for the passage of a second fluid in an alternating manner. The heat exchanger may also include a support structure that may support the plurality of stacked plates in an edge region to stabilize the second cavity. The plurality of stacked plates may each include a first opening and at least two second openings arranged around the first opening. The heat exchanger may also include a plurality of webs arranged between the at least two second openings. The plurality of webs may define the support structure.

Abstract: A method for operating a communications system, in particular a communications system based on software-defined networking, which has at least one network infrastructure component, in particular an SDN switch, and at least one communications device, the network infrastructure component being developed for forwarding data to and/or from the at least one communications device. The method includes the following steps: allocating the communications device to at least one security zone; specifying at least one forwarding rule for forwarding data by the network infrastructure component to and/or from the communications device, the specification of the forwarding rule taking place under consideration of the security zone.

Abstract: A stacked-plate heat exchanger may include a plurality of stacked plates. The plurality of stacked plates may include a plurality of first stacked plates and a plurality of second stacked plates stacked alternately one on top of another. Pairs of adjacent stacked plates may each delimit one of a first cavity for the passage of a first fluid and a second cavity for the passage of a second fluid in an alternating manner. The heat exchanger may also include a support structure that may support the plurality of stacked plates in an edge region to stabilize the second cavity. The plurality of stacked plates may each include a first opening and at least two second openings arranged around the first opening. The heat exchanger may also include a plurality of webs each arranged between two adjacent second openings. The plurality of webs may form the support structure.