Abstract: An on-chip inductor structure includes a conductive inductor coil and a helical ferromagnetic inductor core that is formed to wrap around the conductive coil. The coil is space-apart from the ferromagnetic core by intervening dielectric material. The helical core structure includes at least one magnetic gap lithographically formed in the core.

Abstract: A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) meter, with which the resistance of the strip of ferromagnetic material over a range of measurement signal frequencies is determined based upon the measured impedance values. The measured impedance values, measurement signal frequencies and selected permeability values are then used in numerical simulations to produce multiple resistance versus frequency curves each of which corresponds to one of the selected permeability values.

Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.

Abstract: Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.

Abstract: The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements.

Abstract: The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive a plurality of pulsed input signals having a predetermined duty cycle and a plurality of inductor windings associated with each of the plurality of regulator circuits respectively. The integrated circuit also includes a core array having a plurality of core elements. The plurality of core elements are positioned adjacent to and magnetically coupled with one or more of the plurality of inductor windings. An output node is electrically coupled to the plurality of inductor windings. The output signal at the output node is the sum of the instantaneous voltage on each of the inductor windings associated with the plurality of regulator circuits respectively.