Abstract: A system and method for checking and correcting soft errors in a next instruction pointer is described. In one embodiment, a parity bit is generated for a next instruction pointer that is produced in a front end of a processor. The next instruction pointer and the parity bit are staged from the front end of the processor to a back end of the processor. Another next instruction pointer is generated in the back end of the processor when an instruction corresponding to the next instruction pointer generated in the front end executes. The next instruction pointer generated in the back end is also parity protected. The next instruction pointer generated in the front end is checked for a parity error. The next instruction pointer generated in the back end is also checked for the parity error. Finally, both next instruction pointers are compared to determine if both are equal.

Abstract: A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to the type of code segment to be executed. When the processor is in high performance mode, the dual execution cores operate in lock step on identical instructions, and the execution results generated by each execution core are compared to detect any errors. In high performance monde, the dual execution cores operate independently.

Abstract: A technique to detect and correct corruption of instructions by soft errors. A parity bit is propagated with an instruction through the instruction flow path and checked at selected places. When a parity error is detected, a replay circuit is used to perform a replay to reload the instruction to remove the corrupted instruction.