Patents by Inventor Andres Robert Teene

Andres Robert Teene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for visualizing and analyzing resistance networks
    Patent number: 6854103
    Abstract: An apparatus and method for automatically generating a visual representation of a resistance network and an equivalent point to point resistance for any set of terminals on the resistance network are provided. With the apparatus and method, a cell layout is input to a resistance/capacitance (RC) extraction tool. The RC extraction tool extracts the RC parasitics from the cell layout and inputs them into a resistance network visualization and analysis tool. From the RC parasitics, a graph data structure representation of the resistance network is generated. The graph data structure of the resistance network may then be reduced using, for example, a single layer series and parallel reduction, all layers series and parallel reduction, layer specific reduction, or the like. Following reduction, if any, a visual representation of the resistance network is generated using the graph data structure. Thereafter, equivalent point to point resistance for any set of terminals on the resistance network may be generated.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: February 8, 2005
    Assignee: LSI Logic Corporation
    Inventor: Andres Robert Teene
  • Apparatus and method for visualizing and analyzing resistance networks
    Publication number: 20040128637
    Abstract: An apparatus and method for automatically generating a visual representation of a resistance network and an equivalent point to point resistance for any set of terminals on the resistance network are provided. With the apparatus and method, a cell layout is input to a resistance/capacitance (RC) extraction tool. The RC extraction tool extracts the RC parasitics from the cell layout and inputs them into a resistance network visualization and analysis tool. From the RC parasitics, a graph data structure representation of the resistance network is generated. The graph data structure of the resistance network may then be reduced using, for example, a single layer series and parallel reduction, all layers series and parallel reduction, layer specific reduction, or the like. Following reduction, if any, a visual representation of the resistance network is generated using the graph data structure. Thereafter, equivalent point to point resistance for any set of terminals on the resistance network may be generated.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventor: Andres Robert Teene