Patents by Inventor Andrew B. Hastings

Andrew B. Hastings has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7933875
    Abstract: A distributed file system is disclosed which may include one or more input/output (I/O) nodes and one or more compute nodes. The I/O nodes and the compute nodes may be communicably coupled through an interconnect. Each compute node may include applications to perform specific functions and perform I/O functions through libraries and file system call handlers. The file system call handlers may be capable of providing application programming interfaces (APIs) to facilitate communication between the plurality of I/O nodes and the applications. The file system call handlers may use a message port system to communicate with other compute nodes.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 26, 2011
    Assignee: Sun Microsystems, Inc.
    Inventors: Harriet G. Coverston, Anton B. Rang, Brian D. Reitz, Andrew B. Hastings
  • Patent number: 7757049
    Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: July 13, 2010
    Assignee: Oracle America, Inc.
    Inventors: Andrew B. Hastings, Anton B. Rang, Alok N. Choudhary
  • Patent number: 7647471
    Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: January 12, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew B. Hastings, Alok N. Choudhary, Harriet G. Coverston
  • Patent number: 7606934
    Abstract: A method for routing an incoming service request is described wherein the service request is routed to a selected storage tier based on that selected storage tier having a predicted value indicating a state having greater utility as compared with the predicted value of the state associated with at least one other storage tier within the storage system. A computer system comprising a multi-tier storage system is described, the multi-tier storage system having a routing algorithm configured to adaptively tune functions which map variables describing the state of each storage tier of the storage system into the average latency experienced by incoming service requests associated with the storage tier.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: October 20, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: David Vengerov, Harriet G. Coverston, Anton B. Rang, Andrew B. Hastings
  • Patent number: 7577816
    Abstract: The present invention provides a method of initializing shared memory in a multinode system. The method includes building a local address space in each of a plurality of nodes and exporting the local address space from each of the plurality of nodes to a Remote Translation Table (RTT) in each of the plurality of nodes. The present invention further provides system including a plurality of nodes, each node having one or more processors and a memory controller operatively coupled to the one or more processors, wherein the memory controller includes a RTT for holding translation information for an entire virtual memory address space for the node, further wherein the RTT is initialized upon the start of a process by building a local address space in the node, and exporting the local address space from the node to a RTT in each of the plurality of other nodes.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: August 18, 2009
    Assignee: Cray Inc.
    Inventors: Kitrick Sheets, Andrew B. Hastings
  • Patent number: 7539709
    Abstract: A method and apparatus for managing data is described which includes determining the current state of a storage tier of a plurality of storage tiers within a storage system. Further, a prediction is made, using a prediction architecture comprising at least one predetermined variable, of the utilities of future expected states for at least two of a plurality of storage tiers involved with a data operation, wherein a future expected state of a corresponding storage tier is based on conditions expected to occur following the completion of the data operation. Finally, the data operation is performed if the predicted utility of the future expected state associated with the at least two of a plurality of storage tiers is more beneficial than the utility of the current state.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 26, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: David Vengerov, Harriet G. Coverston, Anton B. Rang, Andrew B. Hastings
  • Patent number: 7519782
    Abstract: In one embodiment, a method and apparatus for ring optimization for data sieving writes is disclosed. The method includes dividing a file range to be written to via a data sieving write operation into N groups, where N is greater than or equal to a number of processes writing to the memory, determining an offset assigned to each process, the offset being a distance from a beginning of the file range at which each process starts its writing, simultaneously writing by each process to the group of the file range determined by the associated offset of each process, and moving, by each process, to the next available subsequent group when a process completes the writing. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 14, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Anton B. Rang, Andrew B. Hastings
  • Patent number: 7503048
    Abstract: Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating system, the thread is associated with the process. Further, a plurality of streams within the thread are selected for execution on a multiple processor unit. Upon the occurrence of a context shifting event, one of the streams enters a kernel mode. If the first stream to enter kernel mode must block, then the execution of the other streams of the plurality of streams is also blocked.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: March 10, 2009
    Assignee: Cray Incorporated
    Inventors: Kitrick Sheets, Josh Williams, Jonathan Gettler, Steve Piatz, Andrew B. Hastings, Peter Hill, James G. Bravatto, James R. Kohn, Greg Titus
  • Patent number: 7475220
    Abstract: A system includes a memory, a plurality of pages held in the memory, an instruction translation look aside buffer (ITLB), a first data translation look aside buffer (DTLB), and a translation look aside (TLB) miss handler. The system also includes an executable/non-executable (x) indicator associated with each page in memory. The TLB miss handler sets the x-indicator for a particular page to indicate “non-executable” when that page is accessed in a mode that allows writing to that page. The ITLB or the ITLB miss handler refuses to allow instructions from a page with an associated x-indicator of “non-executable” to be loaded into the instruction buffer.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: January 6, 2009
    Assignee: Cray Incorporated
    Inventor: Andrew B. Hastings
  • Publication number: 20080120476
    Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.
    Type: Application
    Filed: November 17, 2006
    Publication date: May 22, 2008
    Applicant: Sun Microsystems, Inc.
    Inventors: Andrew B. Hastings, Anton B. Rang, Alok N. Choudhary
  • Publication number: 20080120474
    Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.
    Type: Application
    Filed: November 17, 2006
    Publication date: May 22, 2008
    Applicant: Sun Microsystems, Inc.
    Inventors: Andrew B. Hastings, Alok N. Choudhary, Harriet G. Coverston
  • Publication number: 20080052475
    Abstract: In one embodiment, a method and apparatus for ring optimization for data sieving writes is disclosed. The method includes dividing a file range to be written to via a data sieving write operation into N groups, where N is greater than or equal to a number of processes writing to the memory, determining an offset assigned to each process, the offset being a distance from a beginning of the file range at which each process starts its writing, simultaneously writing by each process to the group of the file range determined by the associated offset of each process, and moving, by each process, to the next available subsequent group when a process completes the writing. Other embodiments are also disclosed.
    Type: Application
    Filed: August 24, 2006
    Publication date: February 28, 2008
    Inventors: Anton B. Rang, Andrew B. Hastings
  • Publication number: 20080052293
    Abstract: A distributed file system is disclosed which may include one or more input/output (I/O) nodes and one or more compute nodes. The I/O nodes and the compute nodes may be communicably coupled through an interconnect. Each compute node may include applications to perform specific functions and perform I/O functions through libraries and file system call handlers. The file system call handlers may be capable of providing application programming interfaces (APIs) to facilitate communication between the plurality of I/O nodes and the applications. The file system call handlers may use a message port system to communicate with other compute nodes.
    Type: Application
    Filed: August 24, 2006
    Publication date: February 28, 2008
    Inventors: Harriet G. Coverston, Anton B. Rang, Brian D. Reitz, Andrew B. Hastings
  • Patent number: 7181587
    Abstract: Virtual memory is mapped to physical memory in a computerized system. Two or more contiguous pages in virtual memory to be mapped to physical memory are identified, and the size in pages of the two or more contiguous pages is determined. An alignment in pages is determined for the two or more contiguous pages of virtual memory, and a free bit data structure is searched to locate a free section of contiguous physical memory having the desired size and alignment. The two or more pages of virtual memory are then mapped via a single mapping to located free section of contiguous physical memory.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: February 20, 2007
    Assignee: Cray Inc.
    Inventor: Andrew B. Hastings