Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Abstract: A method, apparatus, and structure are provided for implementing selective rework for chip stacks. A backside metal layer to create resistive heating is added to a chip backside in a chip stack. A rework tool applies a predefined current to the backside metal layer to reflow solder connections and enables separating selected chips in the chip stack.

Abstract: A method, apparatus, and structure are provided for implementing selective rework for chip stacks. A backside metal layer to create resistive heating is added to a chip backside in a chip stack. A rework tool applies a predefined current to the backside metal layer to reflow solder connections and enables separating selected chips in the chip stack.

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract: A method for calibrating resistors on an integrated circuit chip via a daisy chain scheme. The method comprises the step of configuring one or more links of the daisy chain scheme, wherein each of the one or more links comprises one or more master resistors and one or more slave resistors. The method further comprises the steps of calibrating at least one on-chip reference resistor, the one or more master resistors, and the one or more slave resistors via the daisy chain scheme. The method using the daisy chain scheme enables resistance of at least one off-chip reference resistor to be duplicated to multiple distant locations while maintaining a low mismatch error.

Abstract: A method, system and computer program product for preventing execution of pirated software. A file is loaded on an end user's computer containing a binary image that is generated by removing one or more code bits from an executable code. A request is sent to a remote server to return a software key required for execution of the executable code from the binary image. The software key is downloaded to the end user's computer on which the binary image is loaded. One or more bits from the software key is inserted into the appropriate location of the binary image to regenerate the executable code. The executable code is enabled for execution on the end user's computer only following the embedding of the one or more bits.

Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Abstract: Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process.

Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction minor arrays on the substrate, each diffraction minor array of the set of at least three diffraction minor arrays comprising a single row of minors, all mirrors in any particular diffraction minor array spaced apart a same distance, minors in different diffraction minor arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction minor arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.

Abstract: A method, system and computer program product for partitioning the binary image of a software program, and partially removing code bits to create an encrypted software key, to increase software security. The software program's binary image is partitioned along a random segment length or a byte/nibble segment length, and the code bits removed, and stored, along with their positional data in a software key. The software key is encrypted and is separately distributed from the inoperable binary image to the end user. The encrypted key is stored on a secure remote server. When the end user properly authenticates with the developer's remote servers, the encrypted security key is downloaded from the secure remote server and is locally decrypted. The removed code bits are reinserted into the fractioned binary image utilizing the positional location information. The binary image is then operable to complete execution of the software program.

Abstract: A method, structure, system of aligning a substrate to a photomask. The method comprising: directing light through a clear region of the photomask in a photolithography tool, through a lens of the tool and onto a set of at least three diffraction mirror arrays on the substrate, each diffraction mirror array of the set of at least three diffraction mirror arrays comprising a single row of mirrors, all mirrors in any particular diffraction mirror array spaced apart a same distance, mirrors in different diffraction mirror arrays spaced apart different distances; measuring an intensity of light diffracted from the set of at least three diffraction mirror arrays onto an array of photo detectors; and adjusting a temperature of the photomask or photomask and lens based on the measured intensity of light.