Abstract: An information handling system includes a memory controller and a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device. The DRAM device is configured to detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device, determine if the ECC bit error results in an ECC error threshold being exceeded, and provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded.

Abstract: A vehicle includes an electric motor and an engine selectively coupled to the electric motor. The vehicle has an electric motor controller configured to, in response to (i) an absence of receiving a motor command signal within a predetermined time, (ii) a battery voltage being below a first threshold and (iii) a motor speed exceeding a second threshold, restrict operation of the electric motor to a limited operating mode and control the electric motor to generate a charging torque for a battery.

Abstract: An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.

Abstract: A differential pair group equalization system includes a board providing a differential trace pair group with a plurality of differential trace pairs, each of a transmitter device and a receiver device are coupled to the board and the differential trace pairs in the differential trace pair group. At least one of the transmitter device and the receiver device operates to identify a first differential trace pair in the differential trace pair group, and adjust second differential trace pair equalization parameters for a second differential trace pair in the differential trace pair group. If it is determined that first differential trace pair signal transmission capabilities for the first differential trace pair have improved in response to the adjustment of the second differential trace pair equalization parameters for the second differential trace pair the second differential trace pair equalization parameters are set for the second differential trace pair.

Abstract: A non-volatile dual in-line memory module (NVDIMM) includes a dynamic random access memory (DRAM) block, a plurality of non-volatile random access memory (NVRAM) blocks, and an NVDIMM controller. The DRAM block is organized into a number (N) of pages. Each NVRAM block is organized into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks. The NVDIMM controller is configured to copy first data from a first page of a first NVRAM block to an associated first page of the DRAM block.

Abstract: An information handling system may include a field-programmable gate array (FPGA), and a hypervisor to manage virtual machines. The hypervisor may host a first FPGA service manager that loads instances of binary images for FPGA services into respective regions of the FPGA for the benefit of software applications. The virtual machine may host a second FPGA service manager that receives a request for an FPGA service from a software application running in the virtual machine, and sends a query to the first FPGA service manager to determine whether a binary image for the FPGA service exists on the FPGA. The first FPGA service manager may receive the query and, if a binary image instance for the FPGA service exists on the FPGA, may provide information to the second FPGA service manager to facilitate the use of the FPGA service by the software application running in the virtual machine.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a failure analysis module comprising a program of instructions, the failure analysis module configured to, when read and executed by the processor, set a predictive failure threshold for each of the plurality of non-volatile memories based at least on functional parameters of such non-volatile memory, and adapt the predictive failure threshold for each of the plurality of non-volatile memories based at least on health status parameters of such non-volatile memory.

Abstract: An information handling system includes a top of rack having a port, and a server having a network interface card and a controller. The port of the top of the rack transmits a link aggregation control protocol (LACP) packet. The network interface card receives the LACP packet from the port of the top of rack, and forwards the LACP packet. The controller receives the LACP packet from the network interface card, and to determine whether to update or create a bond associated with the port and a destination virtual machine of the LACP packet. The LACP packet is transmitted from the bond to the network interface card, and in response to the LACP packet being received at the network interface card, the LACP packet is provided to the destination virtual machine.

Abstract: An information handling system may include a field-programmable gate array (FPGA) and an FPGA service manager, within a hypervisor, to receive from software running in a virtual machine a request for an FPGA service, load a bitstream for the service into a first region of the FPGA, increment a count of concurrent users of the bitstream, determine, subsequent to a further update to the count, whether the count is zero or non-zero, and reclaim the first region of the FPGA if the count is zero. The bitstream may be received from the virtual machine or from a catalog of bitstreams maintained on the hypervisor. The FPGA service manager may load a second instance of the bitstream into a second region of the FPGA dependent on execution constraints specified in a bitstream header, or may load a bitstream for a second service into the second region of the FPGA.

Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.

Abstract: An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

Abstract: A non-volatile dual in-line memory module (NVDIMM) includes a dynamic random access memory (DRAM) block, a plurality of non-volatile random access memory (NVRAM) blocks, and an NVDIMM controller. The DRAM block is organized into a number (N) of pages. Each NVRAM block is organized into the number (N) of pages, each page of the DRAM block being N-way set associatively associated with a page of each of the NVRAM blocks. The NVDIMM controller is configured to copy first data from a first page of a first NVRAM block to an associated first page of the DRAM block.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

Abstract: A processor includes a cache memory and a cache controller. The cache controller fetches first data from a first location of an information handling system, stores the first data to a first cache line of a plurality of cache lines, determines first proximity information for the first data based upon the first location, stores the first proximity information in a first proximity tag associated with the first cache line, and evicts the first cache line from the cache based upon the first proximity tag.

Abstract: In one or more embodiments, one or more systems, processes, and/or methods may utilize a trace unit that stores trace data via a trace buffer in a memory medium and may utilize a network interface that provides the trace data from the trace buffer to a network. In one example, the network interface may provide the trace data from the trace buffer to the network in response to a trigger. In one instance, the trigger may include a modification of a pointer to an address of the trace buffer. In another instance, the trigger may include an expiration of a timer. In another example, the trace unit may filter the trace data. In one or more embodiments, storing the traced data and providing the trace data to the network may be performed without involving a main processor of an information handling system that includes the trace unit.

Abstract: A vehicle includes a battery control module and a controller. The battery control module is configured to issue at regular intervals a message indicative of a state of charge (SOC) of a battery. The controller is configured to, in an absence of receiving the messages at the regular intervals while in a key-on state and a torque demand is present, restrict power flow between the battery and an electric powertrain to a limit that is based on a predicted SOC to provide limited propulsive force.

Abstract: In one or more embodiments, an information handling system (IHS) may receive, from another IHS via a first network, a dynamic host configuration protocol discovery request, provide, via the first network, a first Internet protocol version four (IPv4) address to the other IHS, and associate a first Internet protocol version six (IPv6) address. The IHS may receive a domain name service (DNS) lookup request from the first information handling system, provide a multicast DNS (mDNS) request, based at least on logical name information from the DNS lookup request, to a second network, and receive a mDNS response that includes a second IPv6 address associated with the logical name information from the DNS lookup request. In response to receiving the mDNS response, the IHS may configure at least one network address translation configuration that associates that associates the second IPv6 address and a second IPv4 address.

Abstract: A processor includes a cache memory and a cache controller. The cache controller fetches first data from a first location of an information handling system, stores the first data to a first cache line of a plurality of cache lines, determines first proximity information for the first data based upon the first location, stores the first proximity information in a first proximity tag associated with the first cache line, and evicts the first cache line from the cache based upon the first proximity tag.

Abstract: A network adapter, includes a first transceiver module with a transceiver that operates according to a first network protocol and a memory element that includes information that identifies the first network protocol, a second transceiver module with a transceiver that operates according to a second network protocol and a memory element that includes information that identifies the second network protocol, and a controller that reads the information from the first memory element, directs an information handling system to invoke a first network driver associated with the first network protocol based upon the information, reads the second information from the second memory element, and directs the information handling system to invoke a second network driver associated with the second network protocol based upon the second information.