Patents by Inventor Andrew C. Sturges

Andrew C. Sturges has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7437514
    Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: October 14, 2008
    Assignee: STMicroelectronics Limited
    Inventors: Andrew C. Sturges, David May
  • Patent number: 7047399
    Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: May 16, 2006
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Andrew C. Sturges, Nathan M. Sidwell
  • Publication number: 20020078330
    Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions.
    Type: Application
    Filed: April 25, 2001
    Publication date: June 20, 2002
    Applicant: SGS-Thomson Microelectronics Limited
    Inventors: Andrew C. Sturges, Nathan M. Sidwell
  • Publication number: 20020002657
    Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.
    Type: Application
    Filed: August 8, 2001
    Publication date: January 3, 2002
    Applicant: SGS-Thomson Microelectronics Limited
    Inventors: Andrew C. Sturges, David May
  • Patent number: 5961637
    Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Tow instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.
    Type: Grant
    Filed: June 21, 1995
    Date of Patent: October 5, 1999
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Andrew C. Sturges, Nathan M. Sidwell