Patents by Inventor Andrew C. Walton
Andrew C. Walton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11474706Abstract: A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.Type: GrantFiled: April 30, 2013Date of Patent: October 18, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Eric L. Pope, Andrew C. Walton
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Patent number: 10891185Abstract: Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.Type: GrantFiled: August 8, 2014Date of Patent: January 12, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Lidia Warnes, Melvin K. Benedict, Andrew C. Walton
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Patent number: 10824342Abstract: A plurality of mapping modes may be shifted between in real time while maintaining continuous memory mapped access to an application. Data may be migrated between different types storage devices and/or interconnects. The shift between the plurality of mapping modes may be based on a change to the type storage device and/or type of interconnect for the data migration.Type: GrantFiled: February 28, 2014Date of Patent: November 3, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Douglas L Voigt, Andrew C. Walton, Boris Zuckerman
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Patent number: 10810070Abstract: Simulator based detection of a violation of a coherency protocol in an incoherent shared memory system is disclosed. One example is a system including a simulator running on a first computing system, where the simulator simulates a second computing system that is a target for an application to be tested, and where the simulator includes a cache manager to monitor a state of a plurality of simulated caches in an incoherent memory system shared by a plurality of simulated processors, wherein the plurality of simulated processors simulate operations of a respective plurality of processors of the second computing system, and detect a violation of a coherency protocol in the shared memory system, and an alert generator to provide, via a computing device on the first computing system, an alert indicative of the violation.Type: GrantFiled: February 19, 2016Date of Patent: October 20, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Andrew C. Walton, Charles Stuart Johnson, Alexander V. Jizrawi
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Patent number: 10725940Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.Type: GrantFiled: October 22, 2018Date of Patent: July 28, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Chi, Sai Rahul Chalamalasetti, Andrew C. Walton
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Patent number: 10468118Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.Type: GrantFiled: March 3, 2014Date of Patent: November 5, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Andrew C. Walton, Melvin K. Benedict, Eric L. Pope, Erin A. Handgen
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Patent number: 10261852Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.Type: GrantFiled: May 31, 2013Date of Patent: April 16, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Andrew C. Walton
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Publication number: 20190056872Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Ping, Sai Rahul Chalamalasetti, Andrew C. Walton
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Publication number: 20190042341Abstract: Simulator based detection of a violation of a coherency protocol in an incoherent shared memory system is disclosed. One example is a system including a simulator running on a first computing system, where the simulator simulates a second computing system that is a target for an application to be tested, and where the simulator includes a cache manager to monitor a state of a plurality of simulated caches in an incoherent memory system shared by a plurality of simulated processors, wherein the plurality of simulated processors simulate operations of a respective plurality of processors of the second computing system, and detect a violation of a coherency protocol in the shared memory system, and an alert generator to provide, via a computing device on the first computing system, an alert indicative of the violation.Type: ApplicationFiled: February 19, 2016Publication date: February 7, 2019Inventors: Andrew C. Walton, Charles Stuart Johnson, Alexander V. Jizrawi
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Patent number: 10180888Abstract: Example implementations relate to using a spare memory on a memory module. In example implementations, a memory module may have a plurality of memories, including default memories and a spare memory. A plurality of data buffers on the memory module may select data nibbles from the plurality of memories such that when a default memory is identified as defective, a data nibble is selected from the spare memory and not from the defective default memory. A data nibble selected from the default memory may be in a first position in an output of the memory module when the default memory is functional. A data nibble selected from the spare memory may be in a second position in the output of the memory module.Type: GrantFiled: September 27, 2013Date of Patent: January 15, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K Benedict, Eric L Pope, Andrew C. Walton
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Patent number: 10108351Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.Type: GrantFiled: June 23, 2016Date of Patent: October 23, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Chi, Sai Rahul Chalamalasetti, Andrew C. Walton
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Patent number: 10068661Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.Type: GrantFiled: March 6, 2018Date of Patent: September 4, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Lidia Warnes, Melvin K Benedict, Andrew C Walton
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Publication number: 20180204631Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.Type: ApplicationFiled: March 6, 2018Publication date: July 19, 2018Inventors: Lidia WARNES, Melvin K. BENEDICT, Andrew C. WALTON
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Patent number: 9941023Abstract: Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile memory on a memory module. PPR data may indicate how many PPRs have been performed on the memory module.Type: GrantFiled: June 26, 2014Date of Patent: April 10, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Lidia Warnes, Melvin K. Benedict, Andrew C. Walton
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Patent number: 9935709Abstract: A method, a system, and a non-transitory computer-readable memory resource containing instructions for transmitting data are provided. In an example, the method includes providing a header signal having a first optical property. The header signal indicates a start of a packet, and has a minimum period between transitions that is less than a frame period of a receiving device and greater than a scanline period of the receiving device. A payload signal of the packet is provided that has a second optical property that is different from the first optical property. The payload signal has a minimum period between transitions that is less than the frame period of the receiving device and greater than the scanline period of the receiving device.Type: GrantFiled: June 22, 2016Date of Patent: April 3, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Andrew C. Walton, Hang Maxime Ung
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Publication number: 20170371561Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.Type: ApplicationFiled: June 23, 2016Publication date: December 28, 2017Inventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Chi, Sai Rahul Chalamalasetti, Andrew C. Walton
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Publication number: 20170373755Abstract: A method, a system, and a non-transitory computer-readable memory resource containing instructions for transmitting data are provided. In an example, the method includes providing a header signal having a first optical property. The header signal indicates a start of a packet, and has a minimum period between transitions that is less than a frame period of a receiving device and greater than a scanline period of the receiving device. A payload signal of the packet is provided that has a second optical property that is different from the first optical property. The payload signal has a minimum period between transitions that is less than the frame period of the receiving device and greater than the scanline period of the receiving device.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Inventors: Andrew C. Walton, Hang Maxime Ung
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Patent number: 9804972Abstract: Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.Type: GrantFiled: March 28, 2013Date of Patent: October 31, 2017Assignee: Hewlett-Packard Enterprise Development LPInventors: Melvin K. Benedict, William James Walker, Andrew C. Walton
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Patent number: 9778982Abstract: Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.Type: GrantFiled: December 9, 2013Date of Patent: October 3, 2017Assignee: Hewlett Packard Enterprise Development LPInventors: Lidia Warnes, Erin A Handgen, Andrew C. Walton
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Publication number: 20170249229Abstract: Examples disclosed herein relate to querying a hardware component for analysis rules. For example, a processor may determine to retrieve an analysis rule associated with a hardware component within a computing system and query the hardware component for an analysis rule associated with the hardware component. The processor may analyze the computing system based on the received analysis rule associated with the first hardware component and a workload to be executed on the computing system.Type: ApplicationFiled: November 20, 2014Publication date: August 31, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Andrew C. WALTON, Timothy F. FORELL, Zhikui WANG