Patents by Inventor Andrew Chanler

Andrew Chanler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111606
    Abstract: Nodes of the cluster receive workload tasks and use a striping algorithm to determine which node in the cluster should process the workload tasks. Workload task allocation within the cluster is dependent on the cluster membership at the time the striping algorithm is implemented. If a node leaves the cluster, the cluster membership is updated, and the striping algorithm is used to reallocate workload tasks assigned to the leaving node to other nodes within the cluster. If a node joins the cluster, cluster membership is updated, and any workload tasks previously assigned to the cluster nodes are allowed to complete before the joining node is able to begin working on workload tasks. Cluster membership changes are updated in a shared global memory, and locally synchronized in connection with particular events, to implement the distributed cluster join management process.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Andrew Chanler, Kevin Tobin, Mathew J. Pilozzi
  • Patent number: 11556391
    Abstract: One or more aspects of the present disclosure relate to service level input/output scheduling to control central processing unit (CPU) utilization. Input/output (I/O) operations are processed with one or more of a first CPU pool and a second CPU pool of two or more CPU pools. The second CPU pool processes I/O operations that are determined to stall any of the CPU cores.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: January 17, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: John Creed, Owen Martin, Andrew Chanler
  • Patent number: 11347636
    Abstract: In a storage system that implements metadata paging, the page free pool is replenished in the background to reduce foreground evictions and associated latency on page-in. A two-level page eviction controller with cascaded proportional, integral, derivative (PID) controllers optimizes the size of the free page pool and optimizes the rate at which pages are freed in the background. By optimizing these two parameters the page eviction controller dynamically maximizes used pages (minimizing free pages) to increase the metadata cache hit ratio. Optimizing the parameters also reduces the chances of foreground page evictions, thereby reducing IO latency, during both steady state and burst page-in requests.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: May 31, 2022
    Assignee: Dell Products L.P.
    Inventors: Andrew Chanler, Mathew Pilozzi
  • Patent number: 11269544
    Abstract: A storage array uses paged metadata. Each storage director has access to a plurality of object storage systems which describe locations of paged metadata in backing storage. Each object storage system includes different types of inodes which describe objects in backing storage. The object storage systems are used to locate and relocate metadata for loading into global memory, and creation and deletion of objects. An object storage system may be selected based on factors including ratio of different inode types, locality of object usage and anticipated object activity level.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 8, 2022
    Assignee: DELL PRODUCTS LP
    Inventors: Philip Miloslavsky, Matthew David Ivester, David Shadmon, Jeffrey Held, Andrew Chanler
  • Patent number: 11169931
    Abstract: Techniques for obtaining metadata may include: receiving, by a director, an I/O operation directed to a target offset of a logical device, wherein the director is located on a board including a local page table used by components on the board; querying the local page table for a global memory address of first metadata for the target offset of the logical device; and responsive to the local page table not having the global memory address of the first metadata for the target offset of the logical device, using at least a first indirection layer to obtain the global memory address of the first metadata. The global memory may be a distributed global memory including memory segments from multiple different boards each including its own local page table. Compare and swap operations may be used to perform atomic operations to ensure synchronized access when updating the distributed global memory.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: November 9, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Kevin Tobin
  • Publication number: 20210286716
    Abstract: In a storage system that implements metadata paging, the page free pool is replenished in the background to reduce foreground evictions and associated latency on page-in. A two-level page eviction controller with cascaded proportional, integral, derivative (PID) controllers optimizes the size of the free page pool and optimizes the rate at which pages are freed in the background. By optimizing these two parameters the page eviction controller dynamically maximizes used pages (minimizing free pages) to increase the metadata cache hit ratio. Optimizing the parameters also reduces the chances of foreground page evictions, thereby reducing IO latency, during both steady state and burst page-in requests.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Applicant: EMC IP HOLDING COMPANY LLC
    Inventors: Andrew Chanler, Mathew Pilozzi
  • Publication number: 20210117240
    Abstract: One or more aspects of the present disclosure relate to service level input/output scheduling to control central processing unit (CPU) utilization. Input/output (I/O) operations are processed with one or more of a first CPU pool and a second CPU pool of two or more CPU pools. The second CPU pool processes I/O operations that are determined to stall any of the CPU cores.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Applicant: EMC IP Holding Company LLC
    Inventors: John Creed, Owen Martin, Andrew Chanler
  • Publication number: 20200019511
    Abstract: Techniques for obtaining metadata may include: receiving, by a director, an I/O operation directed to a target offset of a logical device, wherein the director is located on a board including a local page table used by components on the board; querying the local page table for a global memory address of first metadata for the target offset of the logical device; and responsive to the local page table not having the global memory address of the first metadata for the target offset of the logical device, using at least a first indirection layer to obtain the global memory address of the first metadata. The global memory may be a distributed global memory including memory segments from multiple different boards each including its own local page table. Compare and swap operations may be used to perform atomic operations to ensure synchronized access when updating the distributed global memory.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Applicant: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Kevin Tobin
  • Patent number: 10534558
    Abstract: A storage array uses paged metadata. Each storage director has access to a plurality of object storage systems which describe locations of paged metadata in backing storage. Each object storage system includes different types of inodes which describe objects in backing storage. The object storage systems are used to locate and relocate metadata for loading into global memory, and creation and deletion of objects. An object storage system may be selected based on factors including ratio of different inode types, locality of object usage and anticipated object activity level.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 14, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Philip Miloslavsky, Matthew David Ivester, David Shadmon, Jeffrey Held, Andrew Chanler
  • Patent number: 10482029
    Abstract: Techniques for obtaining metadata may include: receiving, by a director, an I/O operation directed to a target offset of a logical device, wherein the director is located on a board including a local page table used by components on the board; querying the local page table for a global memory address of first metadata for the target offset of the logical device; and responsive to the local page table not having the global memory address of the first metadata for the target offset of the logical device, using at least a first indirection layer to obtain the global memory address of the first metadata. The global memory may be a distributed global memory including memory segments from multiple different boards each including its own local page table. Compare and swap operations may be used to perform atomic operations to ensure synchronized access when updating the distributed global memory.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Kevin Tobin
  • Patent number: 10365847
    Abstract: A storage array uses paged metadata. Each storage director has access to a plurality of object storage systems which describe locations of paged metadata in backing storage. Each object storage system includes different types of inodes which describe objects in backing storage. The object storage systems are used to locate and relocate metadata for loading into global memory, and creation and deletion of objects. An object storage system may be selected based on factors including ratio of different inode types, locality of object usage and anticipated object activity level.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 30, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Philip Miloslavsky, Matthew David Ivester, David Shadmon, Jeffrey Held, Andrew Chanler
  • Patent number: 10102147
    Abstract: In a system in which a plurality of computing elements share a cache, each computing element owns a stripe of the cache. Each stripe contains cache objects that are accessible to all computing elements but managed only by the owning computing element. Each computing element maintains an LRU FIFO queue in local memory for the cache objects owned by that computing element. Each computing element also maintains a separate hash table in local memory for each other computing element. The hash tables indicate access to cache objects that are owned by those other computing elements. Each computing element updates its LRU FIFO queue when it accesses cache objects that it owns. The hash tables are periodically distributed by all computing elements via RDMA so that the LRU FIFO queues of all computing elements can be updated based on accesses to owned cache objects by other non-owner computing elements.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 16, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel BenHanokh, Andrew Chanler, Felix Shvaiger, Hongliang Tang, Arieh Don
  • Patent number: 10019359
    Abstract: Described are techniques for processing I/O operations. A read operation is received to read first data from a first location. It is determined whether the read operation is a read miss and whether non-location metadata for the first location is stored in cache. Responsive to determining that the read operation is a read miss and that the non-location metadata for the first location is not stored in cache, first processing is performed that includes issuing concurrently a first read request to read the first data from physical storage and a second read request to read the non-location metadata for the first location from physical storage.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 10, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Michael Scharland, Gabriel BenHanokh, Arieh Don
  • Patent number: 9836243
    Abstract: Described are techniques for caching metadata. At least a portion of the cached metadata may be stored persistently on flash-based storage. A data movement granularity size may be determined in accordance with one or more values including M denoting a number of storage units, or more generally metadata objects, having associated metadata stored in a single cached metadata page. At least a portion of the associated metadata is stored on the flash-based storage. A first data portion selected for data movement may have a size equal to the data movement granularity size. The first data portion has first metadata stored on the flash-based storage. The first metadata may include location metadata updated in connection with data movements performed. In accordance with data movement of the first data portion, the first metadata is updated. In a single write operation, the updated first metadata may be written to the flash-based storage.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: December 5, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Michael J. Scharland, Gabriel BenHanokh, Arieh Don
  • Patent number: 9766980
    Abstract: Individual storage devices of a RAID group are monitored for faults. A health indicator for each storage device is calculated based on fault growth rate. Non-failed storage device are swapped out based on the health indicator. Techniques for monitoring the storage devices include background media scans and growth list polling.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 19, 2017
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Krishnamoorthy Anantharaman, Michael D. Garvey, Andrew Chanler, Dale Elliott, Stephen Richard Ives, Prakash Venkatanarayanan, Kevin E. Granlund, Edward S. Robins
  • Patent number: 9678869
    Abstract: Described are techniques for processing I/O operations. A read operation is received to read first data from a first location. It is determined whether the read operation is a read miss and whether non-location metadata for the first location is stored in cache. Responsive to determining that the read operation is a read miss and that the non-location metadata for the first location is not stored in cache, first processing is performed that includes issuing concurrently a first read request to read the first data from physical storage and a second read request to read the non-location metadata for the first location from physical storage.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 13, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew Chanler, Michael Scharland, Gabriel BenHanokh, Arieh Don
  • Patent number: 8910031
    Abstract: A block CRC based fast data hash provides efficient data integrity verification functions. A hash word is generated from block CRCs that are stored along with data blocks in a hard drive for each data and/or parity track of a storage system, such as a RAID array. Each storage system member writes the hash word into a global memory. Thereafter, a director verifies data integrity using all member's hash words with one or more XOR operations. Use of the hash words for data integrity verification saves system bandwidth and CPU processing resources.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 9, 2014
    Assignee: EMC Corporation
    Inventors: ZhiGang Liu, Dale Elliott, Stephen Richard Ives, Shen Liu, Andrew Chanler