Patents by Inventor Andrew Christopher Rose
Andrew Christopher Rose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11314658Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses.Type: GrantFiled: April 28, 2016Date of Patent: April 26, 2022Assignee: Arm LimitedInventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
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Patent number: 10936504Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).Type: GrantFiled: April 28, 2016Date of Patent: March 2, 2021Assignee: ARM LimitedInventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
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Patent number: 10838877Abstract: A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.Type: GrantFiled: April 26, 2016Date of Patent: November 17, 2020Assignee: ARM LimitedInventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose, Matthew Lucien Evans
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Patent number: 10802729Abstract: A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.Type: GrantFiled: April 26, 2016Date of Patent: October 13, 2020Assignee: ARM LimitedInventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
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Patent number: 10621103Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory.Type: GrantFiled: December 5, 2017Date of Patent: April 14, 2020Assignee: Arm LimitedInventors: Andrew Christopher Rose, Richard Roy Grisenthwaite, Ali Ghassan Saidi
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Patent number: 10558590Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.Type: GrantFiled: April 26, 2016Date of Patent: February 11, 2020Assignee: ARM LimitedInventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose, Matthew Lucien Evans
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Patent number: 10359831Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.Type: GrantFiled: March 2, 2017Date of Patent: July 23, 2019Assignee: ARM LimitedInventors: Ashley John Crawford, Andrew Christopher Rose, Tessil Thomas, David Guillen Fandos
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Publication number: 20190171573Abstract: An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory.Type: ApplicationFiled: December 5, 2017Publication date: June 6, 2019Inventors: Andrew Christopher Rose, Richard Roy Grisenthwaite, Ali Ghassan Saidi
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Patent number: 10078589Abstract: Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.Type: GrantFiled: April 30, 2015Date of Patent: September 18, 2018Assignee: ARM LimitedInventors: Daniel Sara, Antony John Harris, Håkan Lars-Göran Persson, Andrew Christopher Rose, Ian Bratt
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Publication number: 20180173645Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.Type: ApplicationFiled: April 26, 2016Publication date: June 21, 2018Inventors: Jason PARKER, Richard Roy GRISENTHWAITE, Andrew Christopher ROSE, Matthew Lucien EVANS
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Publication number: 20180173641Abstract: A data processing apparatus (20) comprises address translation circuitry (40) to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table (50) comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry (40).Type: ApplicationFiled: April 28, 2016Publication date: June 21, 2018Inventors: Jason PARKER, Richard Roy GRISENTHWAITE, Andrew Christopher ROSE
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Publication number: 20180150413Abstract: A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.Type: ApplicationFiled: April 26, 2016Publication date: May 31, 2018Inventors: Jason PARKER, Richard Roy GRISENTHWAITE, Andrew Christopher ROSE, Matthew Lucien EVANS
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Publication number: 20180150251Abstract: A data processing system comprising: ownership circuitry to enforce ownership rights of memory regions within a physical memory address space, a given memory region having a given owning process specified from among a plurality of processes and independently of privilege level, said given owning process having exclusive rights to control access to said given memory region, wherein said given owning process designates said given memory region as one of: private to said given owning process; and shared between said given owning process and at least one further source of memory access requests.Type: ApplicationFiled: April 26, 2016Publication date: May 31, 2018Applicant: ARM LIMITEDInventors: Jason PARKER, Richard Roy GRISENTHWAITE, Andrew Christopher ROSE
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Publication number: 20180129611Abstract: A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more entries (52) each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses.Type: ApplicationFiled: April 28, 2016Publication date: May 10, 2018Inventors: Jason PARKER, Richard Roy GRISENTHWAITE, Andrew Christopher ROSE
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Publication number: 20170255248Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.Type: ApplicationFiled: March 2, 2017Publication date: September 7, 2017Inventors: Ashley John CRAWFORD, Andrew Christopher ROSE, Tessil THOMAS, David GUILLEN FANDOS
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Patent number: 9619387Abstract: A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.Type: GrantFiled: February 21, 2014Date of Patent: April 11, 2017Assignee: ARM LimitedInventors: Matthew L. Evans, Hakan Lars-Goran Persson, Jason Parker, Gareth Stockwell, Andrew Christopher Rose
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Publication number: 20160321179Abstract: Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.Type: ApplicationFiled: April 30, 2015Publication date: November 3, 2016Inventors: Daniel SARA, Antony John HARRIS, Håkan Lars-Göran PERSSON, Andrew Christopher ROSE, Ian BRATT
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Patent number: 9288258Abstract: An integrated circuit comprising multiple master units and multiple slave units connected via interconnect circuitry utilizes token based node-to-node communication flow management within the interconnect circuitry with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.Type: GrantFiled: October 11, 2011Date of Patent: March 15, 2016Assignee: ARM LimitedInventors: Timothy Charles Mace, Andrew Christopher Rose
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Patent number: 9223677Abstract: A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.Type: GrantFiled: June 11, 2008Date of Patent: December 29, 2015Assignee: ARM LimitedInventors: Andrew Brookfield Swaine, Michael John Williams, David Kevin Hart, Andrew Christopher Rose
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Publication number: 20150242319Abstract: A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.Type: ApplicationFiled: February 21, 2014Publication date: August 27, 2015Applicant: ARM LIMITEDInventors: Matthew L. EVANS, Hakan Lars-Goran PERSSON, Jason PARKER, Gareth STOCKWELL, Andrew Christopher ROSE