Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: Provided are a method, system, and program for an adaptor to read and write to system memory. A plurality of blocks of data to write to storage are received at an adaptor. The blocks of data are added to a buffer in the adaptor. A determination is made of pages in a memory device and I/O requests are generated to write the blocks in the buffer to the determined pages, wherein two I/O requests are generated to write to one block split between two pages in the memory device. The adaptor executes the generated I/O requests to write the blocks in the buffer to the determined pages in the memory device.

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract: An apparatus, system, and method are disclosed for mandatory end to end integrity checking. The apparatus includes a compatibility module configured to monitor data from a source and verify integrity information compatibility with a standard, and an integrity module configured to wrap the data from the source with additional integrity information. The system includes a source configured to send data over a network, a target configured to receive data over the network, the apparatus, a main memory module, a storage controller, and a storage device. The method includes monitoring data from a source, verifying integrity information compatibility with a standard, and wrapping the data from the source with additional integrity information.

Abstract: A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.

Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Abstract: An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison module compares an error location indicator with a stored error location indicator. The error location indicator is a location of the correctable bit error. The stored error location indicator includes to at least one previously stored error location indicator of a previously detected correctable bit error. A storage module stores the error location indicator in response to the comparison module determining that the error location indicator differs from a stored error location indicator. A bit error counter module increases a random bit error counter if the comparison module determines that the error location indicator differs from a stored error location indicator and does not increase the random bit error counter otherwise.

Abstract: An apparatus and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.

Abstract: One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

Abstract: A system and method is presented for component failure protection. In one embodiment, the system includes an operational circuit configured to operate in a first operational state, wherein the first operational state is in proximity of a circuit failure threshold. Additionally, the system may include a canary circuit configured to mimic the operational characteristics of the operational circuit, wherein the canary circuit is configured to operate in a second operational state, and wherein the second operational state is in closer proximity of a circuit failure threshold than the proximity of the of the first operational state. The system may also include a variable input control coupled to the operational circuit and the canary circuit, wherein the variable input control is configured to monitor the second operational state and adjust an input to the operational circuit based on the proximity of the second operational state to the circuit failure threshold.

Abstract: An apparatus, system, and method are disclosed for data error checking and recovery in a data storage device. A redundancy check module creates a redundancy check for data on a data storage device in a SCSI End-to-End Checking Standard environment and a redundancy check storage module stores the redundancy check in a guard associated with the data.

Abstract: Protocol multiplexer is configured to receive multiple communication links, each link operating with one of a plurality of communication protocols. Protocol handler converts the received data and frames the data according to the communication protocol in use for a particular communication link. Port multiplexer separates the received frames into data frames and control frames. The data frames being multiplexed onto a single data bus and the control frames being multiplexed onto a single control bus to increase performance of the protocol multiplexer.

Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.

Abstract: An apparatus, system, and method are disclosed for flushing cache data in a cache system. The apparatus includes a zero module and a flush module. The zero module executes an internal processor instruction to zero out a zero memory segment of a nonvolatile memory and a processor cache in response to a loss of primary power to the processor cache. The flush module flushes modified data from an address in the processor cache to a flush memory segment of the nonvolatile memory before the zero module puts a zero in the address. Advantageously, the zero memory segment is reserved within the memory and used to zero out the processor cache, effectively flushing the existing data from the processor cache to a flush memory segment of the memory.

Abstract: A diagnostic tracing logger is presented for use in a multithread environment in which diagnostic trace log entries are captured and recorded. The trace logs are composed of sequences of memory addresses used to access instructions and operands, instruction op-codes and register specifiers, sequences of memory addresses, branch instructions or exceptions, the contents of registers or semiconductor memory locations, and the like. In one embodiment, a software module configures a plurality of buffers to capture bus traces, each trace triggered by a specific pattern. A buffer controller manages transfer of diagnostic trace information from the plurality of buffers to a diagnostic log without using processor memory cycles. The trace information is transferred to a selected buffer using a processor cache flush instruction. Diagnostic trace logging facilitates diagnosis of complex system and software interactions without the cost and overhead of prior art trace logging techniques.

Abstract: An apparatus, system, and method are disclosed for securely providing power supply commands. A security feature is added to the remote management of power-on and power-off sequences. The feature allows for multiple controller nodes to receive a command to initiate a power sequence. Each controller node possesses a unique identifier. The nodes compare the received command with received commands of other nodes to confirm that each node received identical power commands. The security feature prevents inadvertent power commands from being received and executed by a single controller node. The unique identifier of each node must be provided before execution of the power command occurs.

Abstract: Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are transferred to faster intermediate memory between a requester and the slower main memory. The selected data items are retrieved from the slower main memory into a prefetch read buffer as an intermediate memory prior to any request from the requester for the particular selected and prefetched data. The address and size of the prefetched data is derived from the history, pattern, or trajectory of prior memory reads.