Patents by Inventor Andrew David Tune
Andrew David Tune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240054073Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: Arm LimitedInventors: Andrew David Tune, Sean James Salisbury, Edward Martin McCombs, JR.
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Publication number: 20240055047Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: Arm LimitedInventors: Edward Martin McCombs, JR., Andrew David Tune, Sean James Salisbury, Rahul Mathur, Hsin-Yu Chen, Phani Raja Bhushan Chalasani
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Publication number: 20240004796Abstract: An apparatus comprises an non-inclusive cache (14) configured to cache data and coherency control circuitry (16). The coherency control circuitry is configured to look up the non-inclusive cache in response to a coherent access request from a first requestor (4). In response to determining that the coherent access request can be serviced using data stored in a matching entry of the non-inclusive cache, the coherency control circuitry references snoop-filter information associated with the matching entry to determine whether the first requestor can use the data stored in the matching entry without waiting for a response to a snoop of a coherent cache (8).Type: ApplicationFiled: June 8, 2023Publication date: January 4, 2024Applicant: Arm LimitedInventor: Andrew David Tune
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Publication number: 20230418765Abstract: An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data. [FIG.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Andrew David TUNE, Andrew Brookfield SWAINE
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Patent number: 11314676Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.Type: GrantFiled: November 18, 2015Date of Patent: April 26, 2022Assignee: Arm LimitedInventors: Andrew David Tune, Sean James Salisbury
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Patent number: 11314675Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: GrantFiled: October 22, 2019Date of Patent: April 26, 2022Assignee: Arm LimitedInventors: Guanghui Geng, Andrew David Tune, Daniel Adam Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal
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Patent number: 11288195Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response toType: GrantFiled: March 22, 2019Date of Patent: March 29, 2022Assignee: Arm LimitedInventor: Andrew David Tune
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Patent number: 10956205Abstract: Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorize a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.Type: GrantFiled: January 3, 2017Date of Patent: March 23, 2021Assignee: ARM LimitedInventors: Alistair Crone Bruce, Andrew David Tune
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Patent number: 10938622Abstract: An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location.Type: GrantFiled: May 28, 2019Date of Patent: March 2, 2021Assignee: Arm LimitedInventors: Julian Jose Hilgemberg Pontes, Andrew David Tune, Sean James Salisbury
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Patent number: 10929060Abstract: An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.Type: GrantFiled: July 17, 2018Date of Patent: February 23, 2021Assignee: Arm LimitedInventor: Andrew David Tune
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Publication number: 20200301837Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response toType: ApplicationFiled: March 22, 2019Publication date: September 24, 2020Inventor: Andrew David TUNE
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Patent number: 10771194Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: GrantFiled: May 25, 2018Date of Patent: September 8, 2020Assignee: ARM LimitedInventors: Andrew David Tune, Guanghui Geng, Zheng Xu
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Patent number: 10761561Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.Type: GrantFiled: May 25, 2018Date of Patent: September 1, 2020Assignee: Arm LimitedInventors: Saira Samar Malik, David Joseph Hawkins, Andrew David Tune, Guanghui Geng, Julian Jose Hilgemberg Pontes
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Patent number: 10740269Abstract: Arbitration circuitry is provided for allocating up to M resources to N requesters, where M?2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.Type: GrantFiled: July 17, 2018Date of Patent: August 11, 2020Assignee: ARM LimitedInventor: Andrew David Tune
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Patent number: 10592439Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.Type: GrantFiled: April 17, 2019Date of Patent: March 17, 2020Assignee: ARM LimitedInventors: Andrew David Tune, Peter Andrew Riocreux, Alessandro Grande
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Patent number: 10579469Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: GrantFiled: May 25, 2018Date of Patent: March 3, 2020Assignee: Arm LimitedInventors: Guanghui Geng, Andrew David Tune
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Publication number: 20200050568Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Inventors: Guanghui GENG, Andrew David TUNE, Daniel Adam SARA, Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL
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Publication number: 20200026461Abstract: An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.Type: ApplicationFiled: July 17, 2018Publication date: January 23, 2020Inventor: Andrew David TUNE
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Publication number: 20200026674Abstract: Arbitration circuitry is provided for allocating up to M resources to N requesters, where M?2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.Type: ApplicationFiled: July 17, 2018Publication date: January 23, 2020Inventor: Andrew David TUNE
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Publication number: 20190379573Abstract: An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location.Type: ApplicationFiled: May 28, 2019Publication date: December 12, 2019Inventors: Julian Jose Hilgemberg PONTES, Andrew David TUNE, Sean James SALISBURY