Patents by Inventor Andrew Gaiarsa

Andrew Gaiarsa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10534644
    Abstract: Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local storage mechanism. Each of the plurality of processors of the system may have controlled access to the resource and each of the processors is dedicated to one of a plurality of tasks of an application. The application including the plurality of tasks may be replicated using the processor local storage mechanism, wherein each of the tasks of the replicated application includes an affinity to one of the plurality of processors.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 14, 2020
    Assignee: Wind River Systems, Inc.
    Inventors: Andrew Gaiarsa, Maarten Koning
  • Patent number: 9772960
    Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 26, 2017
    Assignee: WIND RIVER SYSTEMS, INC.
    Inventors: Andrew Gaiarsa, Maarten Koning, Felix Burton
  • Patent number: 9547522
    Abstract: A non-transitory computer-readable storage medium storing a set of instructions that are executable by a processor. The set of instructions, when executed by one or more processors of a multi-processor computing system, causes the one or more processors to perform operations including initiating a first processor of the multi-processor computing system with an operating system image of an operating system, the operating system image including a predetermined object map, initiating a second processor of the multi-processor computing system with the operating system image, placing a plurality of system objects with corresponding processors according to the predetermined object map, receiving a triggering event causing a change to the predetermined object map and relocating one of the system objects to a different one of the processors based on the change to the predetermined object map.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: January 17, 2017
    Assignee: WIND RIVER SYSTEMS, INC.
    Inventor: Andrew Gaiarsa
  • Publication number: 20150293780
    Abstract: A non-transitory computer-readable storage medium storing a set of instructions that are executable by a processor. The set of instructions, when executed by one or more processors of a multi-processor computing system, causes the one or more processors to perform operations including initiating a first processor of the multi-processor computing system with an operating system image of an operating system, the operating system image including a predetermined object map, initiating a second processor of the multi-processor computing system with the operating system image, placing a plurality of system objects with corresponding processors according to the predetermined object map, receiving a triggering event causing a change to the predetermined object map and relocating one of the system objects to a different one of the processors based on the change to the predetermined object map.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 15, 2015
    Applicant: Wind River Systems, Inc.
    Inventor: Andrew GAIARSA
  • Publication number: 20140108690
    Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: Wind River Systems, Inc.
    Inventors: Andrew GAIARSA, Maarten Koning, Felix Burton
  • Publication number: 20110276978
    Abstract: A computer readable storage medium storing a set of instructions executable by a processor. The set of instructions is operable to receive an instruction to reserve a processor of a system including a plurality of processors, receive an instruction to perform a task, determine whether the task has affinity for the reserved processor, execute the task using the reserved processor if the task has affinity for the reserved processor, execute the task using one of the processors other than the reserved processor if the task does not have affinity for the reserved processor.
    Type: Application
    Filed: May 10, 2010
    Publication date: November 10, 2011
    Inventors: Andrew Gaiarsa, Roger Keith Wiles
  • Publication number: 20100332796
    Abstract: Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local storage mechanism. Each of the plurality of processors of the system may have controlled access to the resource and each of the processors is dedicated to one of a plurality of tasks of an application. The application including the plurality of tasks may be replicated using the processor local storage mechanism, wherein each of the tasks of the replicated application includes an affinity to one of the plurality of processors.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Inventors: Andrew Gaiarsa, Maarten Koning
  • Publication number: 20070204271
    Abstract: Described is a system and method for loading a target operating system into a host operating system, wherein the host processing space includes a memory pool, mapping the memory pool into a plurality of processes, scheduling tasks within one of the processes to create a multitasking environment, forking the plurality of processes, sharing the mapped memory pool and the loaded target operating system with the forked plurality of processes, thereby providing the plurality of processes with shared access to the memory pool and managing the scheduled tasks within the multitasking environment.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 30, 2007
    Inventors: Andrew Gaiarsa, Maarten Koning
  • Patent number: 7103745
    Abstract: A computer system is provided comprising a core operating system and a system space having a number of memory locations. The core operating system creates a number of protection domains to partition the system space. Each of the partitions includes a partition operating system and a partition user application. Each partition operating system provides resource allocation services to the respective partition user application within the partition.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: September 5, 2006
    Assignee: Wind River Systems, Inc.
    Inventors: Maarten Koning, Andrew Gaiarsa, Thierry Preyssler
  • Patent number: 6988226
    Abstract: A computer system and method for operating a computer system is provided which comprises a core operating system and a system space having a number of memory locations. The core operating system is arranged to create a number of protection domains to partition the system space into a core operating system space and a plurality of partitions. A partition operating system, a partition user application, and a partition alarm handler is provided in each partition. Each partition operating system provides resource allocation services to the respective partition user application within the partition. An alarm dispatcher and a system alarm handler is provided in the core operating system space. The alarm dispatcher is configured to receive alarms and to dispatch the alarms to one of the alarm handlers.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: January 17, 2006
    Assignee: Wind River Systems, Inc.
    Inventors: Maarten Koning, Kevin McCombe, Vincent Hue, Remi Cote, Thierry Preyssler, Andrew Gaiarsa
  • Patent number: 6904483
    Abstract: A method for controlling priority inheritance in a computer system is described, the method including testing a priority inheritance variable associated with a task, and lowering the current priority of a task when testing the priority inheritance variable indicates that the task holds no resources that are involved in a priority inheritance.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: June 7, 2005
    Assignee: Wind River Systems, Inc.
    Inventors: Maarten Koning, Andrew Gaiarsa
  • Publication number: 20040078799
    Abstract: A computer system and method for operating a computer are provided which includes a core operating system and a system space having a number of memory locations. The core operating system is arranged to create a number of protection domains to partition the system space into a core operating system space and a plurality of partitions. A partition operating system and a partition user application is provided in each partition, and each partition operating system provides resource allocation services to the respective partition user application within the partition. The system also includes an interpartition communication system. The interpartition communication system interacts with the core operating system and each partition operating system to deliver messages between partitions.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 22, 2004
    Inventors: Maarten Koning, Vincent Hue, Thierry Preyssler, Andrew Gaiarsa
  • Publication number: 20020138679
    Abstract: A method for controlling priority inheritance in a computer system is described, the method including testing a priority inheritance variable associated with a task, and lowering the current priority of a task when testing the priority inheritance variable indicates that the task holds no resources that are involved in a priority inheritance.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 26, 2002
    Inventors: Maarten Koning, Andrew Gaiarsa