Abstract: An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.

Abstract: An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.

Abstract: A mixer termination circuit for a downconverter mixer includes a diplexer circuit coupled to an output of the downconverter mixer. The diplexer circuit is configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer.

Abstract: A mixer termination circuit for a downconverter mixer includes a diplexer circuit coupled to an output of the downconverter mixer. The diplexer circuit is configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer.

Abstract: An electronic system for accurately controlling the RF output power from a power amplifier (21) is implemented using a multiplier (28) which multiplies the output power by itself to provide a DC component which is fed to a variable gain amplifier (29) which provides a controlling signal via a comparator (24) and an integrator (25) to the power amplifier. The transfer function between controlling signal and output power is substantially linear, even during dynamic variation of the controlling signal. The system is capable of a large dynamic range, and exhibits constant control loop bandwidth over this range. This is of particular use to TDMA applications with a large dynamic range of levelled output powers because a fixed filter function can be used to shape the transmitted burst.

Abstract: An electronic system for accurately controlling the RF output power from a power amplifier (21) is implemented using a multiplier (28) which multiplies the output power by itself to provide a DC component which is fed to a variable gain amplifier (29) which provides a controlling signal via a comparator (24) and an integrator (25) to the power amplifier. The transfer function between controlling signal and output power is substantially linear, even during dynamic variation of the controlling signal. The system is capable of a large dynamic range, and exhibits constant control loop bandwidth over this range. This is of particular use to TDMA applications with a large dynamic range of levelled output powers because a fixed filter function can be used to shape the transmitted burst.

Abstract: A transmitter to transmit data from an end-point includes a reference oscillator; a low pass filter coupled to the reference oscillator; a modulation filter to provide an over-sampled modulated signal; a synthesizer coupled to the low pass filter and the modulation filter; and a sine wave generator coupled to the synthesizer.

Abstract: A receiver which is capable of receiving in parallel data transmitted at arbitrary frequencies within a radio channel includes: a radio frequency (RF) front end to convert an RF signal to a digitized signal; a Fast Fourier Transform (FFT) generator coupled to the RF front-end to separate the digitized signal into a plurality of sub-channels; a bank of phase locked loops (PLLs) coupled to the FFT generator, each PLL operating on a sub-channel with a sub-channel center; and a flag detector coupled to the bank of PLLs to detect variations from the sub-channel center and to recover the usage data transmitted from the end-point.

Abstract: A remote data collection system for collecting usage data from an endpoint includes a monitoring module coupled to the endpoint, the monitoring module having a wireless transmitter to transmit the usage data. The system also includes a receiver to receive usage data from the wireless transmitter of the monitoring module, the receiver capable of receiving in parallel data transmitted at arbitrary frequencies within a radio channel.