Abstract: A real-time radar surveillance system comprises at least one land-based non-coherent radar sensor apparatus adapted for detecting maneuvering targets and targets of small or low radar cross-section. The radar sensor apparatus includes a marine radar device, a digitizer connected to the marine radar device for receiving therefrom samples of radar video echo signals, and computed programmed to implement a software-configurable radar processor generating target data including detection data and track data, the computer being connectable to a computer network including a database. The processor is figured to transmit at least a portion of the target data over the network to the database, the database being accessible via the network by at least one user application that receives target data from the database, the user application providing a user interface for at least one user of the system.

Abstract: A solidifying prepolymeric implant composition comprising a biocompatible prepolymer and an optional filler. One such implant composition is a polyurethane implant composition comprising an isocyanate, such as hydroxymethylenediisocyanate (HMDI) and an alcohol, such as polycaprolactonediol (PCL diol). The compositions of the invention are useful for improving bone structure in patients by applying the solidifying implant composition to bone, reinforcing bone structure, improving load bearing capacity and/or aiding healing of microfractures.

Abstract: A surgical stapler includes a first stapler half including an anvil surface having a plurality of staple forming pockets, and a second stapler half configured to releasably couple with the first stapler half. The second stapler half is operable to deploy staples toward the anvil surface. The stapler also includes a projection positioned on one of the stapler halves and extending laterally relative to a longitudinal axis of the stapler. The stapler halves are configured to pivot relative to each other about the projection. The stapler further includes a locking member positioned on the other of the stapler halves. The locking member is configured to translate along the longitudinal axis of the stapler between a locked state in which the locking member selectively captures the projection and an unlocked state in which the locking member selectively releases the projection. The locking member is biased proximally toward the locked state.

Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Abstract: A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.