Patents by Inventor Andrew J. Tomlin

Andrew J. Tomlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10657087
    Abstract: A semiconductor storage device includes a controller including a data direct memory access (DDMA) controller. The controller receives a plurality of read commands segmented into data transfer descriptors associated with data tags from a host device and directs a plurality of the data transfer descriptors to the DDMA controller. The DDMA controller pre-fetches one or more descriptors from the host device associated with one or more of the plurality of data tags, a first data tag having an associated number of descriptors corresponding to contiguous blocks of memory. The DDMA controller determines if the associated number of descriptors satisfies a threshold, and, if it does not, moves the first data tag to a first list, when at a head of the first list moves the first data tag to a second list, and when at a head of the second list, transmits the data associated with the first data tag.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Andrew J. Tomlin
  • Publication number: 20190370199
    Abstract: A semiconductor storage device includes a controller including a data direct memory access (DDMA) controller. The controller receives a plurality of read commands segmented into data transfer descriptors associated with data tags from a host device and directs a plurality of the data transfer descriptors to the DDMA controller. The DDMA controller pre-fetches one or more descriptors from the host device associated with one or more of the plurality of data tags, a first data tag having an associated number of descriptors corresponding to contiguous blocks of memory. The DDMA controller determines if the associated number of descriptors satisfies a threshold, and, if it does not, moves the first data tag to a first list, when at a head of the first list moves the first data tag to a second list, and when at a head of the second list, transmits the data associated with the first data tag.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventor: Andrew J. Tomlin
  • Patent number: 10417123
    Abstract: Disclosed embodiments are directed to systems and methods for improving garbage collection and wear leveling performance in data storage systems. The embodiments can improve the efficiency of static wear leveling by picking the best candidate block for static wear leveling and/or postponing static wear leveling on certain candidate blocks. In one embodiment, one or more source blocks for a static wear leveling operation are selected based at least on whether the one or more blocks have a low P/E count and contain static data, such as data that has been garbage collected.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 17, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kamyar Souri, Andrew J. Tomlin, Dmitry S. Obukhov, Jing Booth, Mei-Man L. Syu
  • Patent number: 10254983
    Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Patent number: 10114744
    Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kamyar Souri, Andrew J. Tomlin, Dmitry S. Obukhov, Jing Booth, Mei-Man L. Syu
  • Patent number: 10061696
    Abstract: A method for managing garbage collection of memory locations in an DSD having a plurality of dies each having a plurality of memory blocks includes: selecting a physical region of memory to be garbage collected, the selected physical region being a subset of a block management region; and garbage collecting the selected physical region. The garbage collecting includes: determining one or more journals corresponding to the selected physical region, the journal comprising transaction entries indicating what logical data are written to memory locations in the selected physical region; determining whether the memory locations within the physical region contain valid data based on a comparison of information in the journal and a mapping table; and if valid data exists, copying valid data into memory locations in memory regions other than the selected physical region of memory. The selected physical region of memory is erased when the block management region is erased.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 28, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Justin Jones, Andrew J. Tomlin, Paul Sweazey, Johnny A. Lam, Rodney N. Mullendore
  • Patent number: 10055345
    Abstract: A solid state drive controller includes a processor configured to couple to a plurality of non-volatile memory devices. The plurality of non-volatile memory devices are configured to store a plurality of system journals and a plurality of physical pages. The solid state drive controller also includes a volatile memory configured to store a logical-to-physical address translation map configured to enable the solid state drive controller to determine a physical location of at least one logical page. The processor is configured to maintain the plurality of system journals in the plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of the plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 21, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Andrew J. Tomlin, Rodney N. Mullendore, Justin Jones
  • Publication number: 20170357571
    Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.
    Type: Application
    Filed: April 24, 2017
    Publication date: December 14, 2017
    Inventors: Kamyar SOURI, Andrew J. Tomlin, Dmitry S. Obukhov, Jing Booth, Mei-Man L. Syu
  • Publication number: 20170344287
    Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.
    Type: Application
    Filed: March 14, 2017
    Publication date: November 30, 2017
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Patent number: 9817577
    Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 14, 2017
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Patent number: 9792067
    Abstract: A device may comprise a plurality of non-volatile memory devices configured to store a plurality of physical pages and a controller coupled thereto, configured to program and read data to and from the plurality of non-volatile memory devices. The data may be stored in a plurality of logical pages (L-Pages) of non-zero length at starting addresses within the plurality of physical pages. The controller may be configured to execute first and second commands to indicate that first and second physical locations within the plurality of non-volatile memory devices no longer contain valid data and are now free space. This may be done by carrying out first and second virtual write operations of first and second L-Pages of a predetermined length at first and second unique addresses within a virtual address range that does not correspond to any of the physical pages, and accounting for an amount of free space gained as a result of executing the commands.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 17, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Andrew J. Tomlin
  • Patent number: 9760304
    Abstract: A method of writing data to a range of logical blocks in a storage medium includes: receiving a command including a starting logical block address, a value indicating a range of logical block addresses to be written, and a logical block of data; storing the logical block in a first temporary storage; generating a logical page by duplicating the logical block a plurality of times corresponding to a number of logical blocks in a logical page and transporting the generated logical page to a second temporary storage and storing the generated logical page in the second temporary storage; writing the generated logical page from the second temporary storage into the storage medium beginning from the starting logical block address; and performing a read-modify-write operation if the first write operation does not begin on a logical page boundary or the last write operation does not end on a logical page boundary.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: September 12, 2017
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Jack W. Flinsbaugh, Justin Jones, Rodney N. Mullendore, Andrew J. Tomlin
  • Patent number: 9632926
    Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 25, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kamyar Souri, Andrew J. Tomlin, Dmitry S. Obukhov, Jing Booth, Mei-Man L. Syu
  • Publication number: 20170075807
    Abstract: A solid state drive controller includes a processor configured to couple to a plurality of non-volatile memory devices. The plurality of non-volatile memory devices are configured to store a plurality of system journals and a plurality of physical pages. The solid state drive controller also includes a volatile memory configured to store a logical-to-physical address translation map configured to enable the solid state drive controller to determine a physical location of at least one logical page. The processor is configured to maintain the plurality of system journals in the plurality of non-volatile memory devices, wherein each system journal defines physical-to-logical page correspondences for a predetermined range of the plurality of physical pages, and each system journal comprises an identification number that includes a portion of an address of a first physical page of the predetermined range of the plurality of physical pages.
    Type: Application
    Filed: November 7, 2016
    Publication date: March 16, 2017
    Inventors: Andrew J. TOMLIN, Rodney N. MULLENDORE, Justin JONES
  • Patent number: 9594520
    Abstract: A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 14, 2017
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Andrew J. Tomlin, Justin Jones, Rodney N. Mullendore
  • Publication number: 20170010823
    Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Andrew J. TOMLIN, Justin JONES, Rodney N. MULLENDORE
  • Patent number: 9513831
    Abstract: Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 6, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: James J. Walsh, Andrew J. Tomlin
  • Patent number: 9507523
    Abstract: A data storage device may comprise an array of flash memory devices comprising a plurality of blocks, each comprising a plurality of physical pages. A controller may be coupled to and configured to program and read data from the array responsive to host commands. The controller may be configured to store data in a plurality of logical pages (L-Pages) of different sizes, each associated with an L-Page number that is configured to enable the host to logically reference data stored in one or more of the physical pages; and maintain a logical-to-physical address translation map configured to enable the controller to determine a location, within one or more physical pages, of the data referenced by each L-Page number. The translation map may comprise a plurality of mapping entries arranged by L-Page numbers, each comprising a complete starting physical address of an L-Page within one of the physical pages.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 29, 2016
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Rodney N. Mullendore, Radoslav Danilak, Justin Jones, Andrew J. Tomlin
  • Patent number: 9489296
    Abstract: A data storage device may comprise non-volatile memory devices, each configured to store a plurality of physical pages, a controller and a first volatile memory configured to store a logical-to-physical address translation map that enables the controller to determine a physical location of logical pages. The controller may maintain, in the memory devices, a plurality of journals defining physical-to-logical page correspondences, each entry of which associating one or more physical pages to a logical page. Garbage collection may be carried out by reading entries of the journals; determining a validity of each logical page referenced by the read entries through a comparison with a corresponding entry in the map, the logical pages referenced by the read entries being stored in first physical pages; writing logical pages determined to be valid to second physical pages and updating the map accordingly; and designating at least the first physical pages as free space.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 8, 2016
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Andrew J. Tomlin, Rodney N. Mullendore, Justin Jones
  • Publication number: 20160313936
    Abstract: A method for writing data in a data storage device includes: writing data to a physical memory location in a non-volatile memory; writing, for a first time, to a location in a volatile memory corresponding to a logical address of the data, a physical address of the physical memory location of the non-volatile memory containing the data; and writing, for a second time, to the location in the volatile memory corresponding to the logical address of the data, the address of the physical memory location of the non-volatile memory containing the data. The physical address of the physical memory location is written with appended error detection code information, and the error detection code information is determined based on the logical address of the data.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 27, 2016
    Inventors: Justin JONES, Andrew J. TOMLIN, Rodney N. MULLENDORE