Patents by Inventor Andrew Jarabek

Andrew Jarabek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8848533
    Abstract: The present disclosure provides a fabric ingress scheduler and method that distributes ingress packet traffic in a time division multiplex (TDM) system, both fabric interface aggregate and per connection, deterministically across fabric paths. Advantageously, the fabric ingress scheduler and method minimizes fabric latency and prevents fabric interface head-of-line blocking. The fabric ingress scheduler and method utilizes the fact that each connection flow has a known maximum rate which must be reserved through the fabric for prevention of data loss (essentially circuit switching using a packet fabric). In exemplary embodiments, the fabric interface supports per packet fabric path selection. Generally, the fabric ingress scheduler and method generally provides a deterministic scheduling of ingress packets to fabric paths.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 30, 2014
    Assignee: Ciena Corporation
    Inventors: David Stuart, Andrew Jarabek, James Tierney
  • Patent number: 7978736
    Abstract: A method and apparatus for efficient provisioning of a VT/TU cross-connect includes checking a state of a control bit that specifies whether to assemble an output from multiple virtual tributary (VT1.5/VT2) or tributary unit (TU11/TU12) connections or handle the output as an synchronous transport signal (STS) or administrative unit (AU-3/AU-4) connection, and switching a predetermined number of entries together based on a state of the control bit.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 12, 2011
    Assignee: Ciena Corporation
    Inventors: Andrew Jarabek, Aris Tombul, Karl Hammermeister
  • Patent number: 7542484
    Abstract: A method and apparatus for managing latency includes receiving data from synchronous transport signals (STS) and virtual tributary (VT) sources, providing a provisioning bit for each output associated with a memory, and adjusting a pointer for the VT sources based on the provisioning bit such that the STS and VT outputs are synchronized.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: June 2, 2009
    Assignee: Nortel Networks Limited
    Inventors: Andrew Jarabek, Aris Tombul
  • Patent number: 7359379
    Abstract: A technique for provisioning cross-connects in network switching environment includes receiving a portion of the an input data stream including having header data and the payload data, the payload data occurring at a first offset relative to the header data and generating a delayed version of the portion of the input data stream. The technique also includes generating a portion of a retimed data stream by selecting between the portion of the input data stream and the delayed version of the portion of the input data stream, the retimed data stream including the header data and the payload data, the payload data occurring at a second offset relative to the header data.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: April 15, 2008
    Assignee: Nortel Networks Limited
    Inventors: Andrew Jarabek, Aris Tombul, Mark Carson, Ho Nguyen
  • Patent number: 7246289
    Abstract: A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a comparison result, and indicating a failure based on the comparison result.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 17, 2007
    Assignee: Nortel Networks Limited
    Inventors: Andrew Jarabek, Aris Tombul, Warren Lau
  • Publication number: 20060233165
    Abstract: A technique for provisioning cross-connects in network switching environment includes receiving a portion of the an input data stream including having header data and the payload data, the payload data occurring at a first offset relative to the header data and generating a delayed version of the portion of the input data stream. The technique also includes generating a portion of a retimed data stream by selecting between the portion of the input data stream and the delayed version of the portion of the input data stream, the retimed data stream including the header data and the payload data, the payload data occurring at a second offset relative to the header data.
    Type: Application
    Filed: September 30, 2003
    Publication date: October 19, 2006
    Inventors: Andrew Jarabek, Aris Tombul, Mark Carson, Ho Nguyen
  • Patent number: 7042913
    Abstract: A technique for provisioning cross-connects in network switching environment includes writing a first set of data into a first memory element during a first time interval and writing a second set of data into a second memory element during a second time interval. The technique reads a portion of the first set of data from the first memory element during the second time interval and reads a portion of the second set of data from the second memory element during a third time interval, and determines the first, second, and third time intervals based on a format of the sets of data, with the first time interval ending before the second time interval begins, and the second time interval ending before the third time interval begins.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 9, 2006
    Assignee: Nortel Networks Limited
    Inventors: Andrew Jarabek, Aris Tombul, Robert Gibbins
  • Publication number: 20050068991
    Abstract: A method and apparatus for managing latency includes receiving data from synchronous transport signals (STS) and virtual tributary (VT) sources, providing a provisioning bit for each output associated with a memory, and adjusting a pointer for the VT sources based on the provisioning bit such that the STS and VT outputs are synchronized.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Andrew Jarabek, Aris Tombul
  • Publication number: 20050071718
    Abstract: A method and apparatus for detecting errors in a memory includes generating a first check word based on incoming data and generating a second check word based on stored data. The method includes comparing the first check word to the second check word, generating a comparison result, and indicating a failure based on the comparison result.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Andrew Jarabek, Warren Lau, Aris Tombul
  • Publication number: 20050071594
    Abstract: A technique for provisioning cross-connects in network switching environment includes writing a first set of data into a first memory element during a first time interval and writing a second set of data into a second memory element during a second time interval. The technique reads a portion of the first set of data from the first memory element during the second time interval and reads a portion of the second set of data from the second memory element during a third time interval, and determines the first, second, and third time intervals based on a format of the sets of data, with the first time interval ending before the second time interval begins, and the second time interval ending before the third time interval begins.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Andrew Jarabek, Aris Tombul, Robert Gibbins
  • Publication number: 20050068988
    Abstract: A method and apparatus for efficient provisioning of a VT/TU cross-connect includes checking a state of a control bit that specifies whether to assemble an output from multiple virtual tributary (VT1.5/VT2) or tributary unit (TU11/TU12) connections or handle the output as an synchronous transport signal (STS) or administrative unit (AU-3/AU-4) connection, and switching a predetermined number of entries together based on a state of the control bit.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Andrew Jarabek, Aris Tombul, Karl Hammermeister