Abstract: A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

Abstract: A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a voltage supply line. When the delay locked loop is configured to operate in response to an input clock signal having a relatively high frequency, the voltage supply line is coupled to receive a first supply voltage. When the delay locked loop is configured to operate in response to an input clock signal having a relatively low frequency, the voltage supply line is coupled to receive a second supply voltage, which is significantly lower than the first supply voltage. When operating in response to the first supply voltage, the delay elements exhibit relatively short delays. Conversely, when operating in response to the second supply voltage, the delay elements exhibit relatively long delays.

Abstract: A phase matched clock divider includes a first feed-through flip-flop that receives a first input clock signal, and in response, provides a first output clock signal having the same frequency. The first feed-through flip-flop is enabled and disabled in response to a first reset signal. A plurality of series-connected flip-flops each receives the first input clock signal, and in response, provides a divided output clock signal. Each of the series-connected flip-flops is enabled and disabled in response to a second reset signal. The first and second release signals asynchronously disable the associated flip-flops in response to a third reset signal. The first release signal synchronously enables the first feed-through flip-flop in response to the third reset signal and a release clock signal. The second release signal enables the series-connected flip-flops in response to the third reset signal and a release control signal.

Abstract: The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. Because the frequencies are spread in 0.5 MHz increments, only three frequencies are included in any 1 MHz window. As a result, ? of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency.

Abstract: Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

Abstract: After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal.

Abstract: A glitchless delay line using a Gray code multiplexer is provided. The glitchless delay line combines a multi-tap delay circuit with the Gray code multiplexer. Specifically, the multi-tap delay circuit provides a plurality-of sequentially ordered delayed output signals on a plurality of sequentially ordered output terminals. The Gray code multiplexer has a plurality of input terminals coupled to the sequentially ordered delayed output terminals. The Gray code multiplexer is controlled by driving a Gray code value onto the control terminals of the Gray code multiplexer to select a specific delayed output terminal of the multi-tap delay circuit. The delay provided by the delay line is increased by incrementing the Gray code value on the control terminals of the Gray code multiplexer and decreased by decrementing the Gray code value on the control terminals. Race conditions on the control lines are eliminated when incrementing or decrementing the Gray code value by one.

Abstract: An input/output interconnect (IOI) circuit is provided for coupling input/output (IO) blocks to an array of configurable logic tiles in a field programmable gate array (FPGA). Each of the tiles includes a configurable logic block and a programmable interconnect structure that includes a plurality of intermediate-length buses. The intermediate-length buses are staggered, such that only a subset of the intermediate-length buses routed by a logic block is connected to the logic block. The IOI circuit includes routing circuits at the perimeter of the array for terminating the intermediate-length buses. In one embodiment, the routing circuits connect various ends of unidirectional intermediate-length buses in a U-turn configuration, thereby making use of all of the intermediate-length buses, and maintaining a regular pattern of intermediate-length buses in the tiles.