Patents by Inventor Andrew K W Leung

Andrew K W Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit board with corner hollows
    Patent number: 9867282
    Abstract: A method of manufacturing is provided that includes singulating a circuit board from a substrate of plural of the circuit boards, wherein the circuit board is shaped to have four corner hollows. The corner hollows may be various shapes.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: January 9, 2018
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Suming Hu, Neil McLellan, Andrew K W Leung, Jianguo Li
  • Circuit board with via trace connection and method of making the same
    Patent number: 9793199
    Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: October 17, 2017
    Assignee: ATI Technologies ULC
    Inventors: Andrew K W Leung, Neil McLellan, Yip Seng Low
  • CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS
    Publication number: 20160126171
    Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Roden Topacio, Andrew K.W. Leung
  • CIRCUIT BOARD WITH CORNER HOLLOWS
    Publication number: 20150049441
    Abstract: A method of manufacturing is provided that includes singulating a circuit board from a substrate of plural of the circuit boards, wherein the circuit board is shaped to have four corner hollows. The corner hollows may be various shapes.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 19, 2015
    Inventors: Suming Hu, Neil McLellan, Andrew K.W. Leung, Jianguo Li
  • Solder mask with anchor structures
    Patent number: 8772083
    Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: July 8, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Andrew K W Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
  • Circuit board with oval micro via
    Patent number: 8445329
    Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor structure. A first via is formed in the first interconnect layer and in electrical contact with the first conductor structure. The first via has a first oval footprint.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: May 21, 2013
    Assignee: ATI Technologies ULC
    Inventors: Andrew K W Leung, Neil McLellan
  • Conductor bump method and apparatus
    Patent number: 8294266
    Abstract: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 23, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Andrew K W Leung
  • Circuit Board with Via Trace Connection and Method of Making the Same
    Publication number: 20110147061
    Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Andrew K.W. Leung, Neil McLellan, Yip Seng Low
  • Conductor bump method and apparatus
    Patent number: 7906424
    Abstract: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: March 15, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Andrew K W Leung
  • Hybrid Semiconductor Chip Package
    Publication number: 20100102457
    Abstract: Various apparatus and method of packaging semiconductor chips are disclosed. In one aspect, a method of manufacturing is provided that includes placing a semiconductor chip package into a mold. The semiconductor chip package includes a substrate that has a side and a first semiconductor chip coupled to the side in spaced apart relation to define a space between the first semiconductor chip and the side. A second semiconductor chip is mounted on the first semiconductor chip. At least one conductor wire is electrically coupled to the second semiconductor chip and the substrate. A molding material is introduced into the mold to flow into the space and establish an underfill and encapsulate the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 29, 2010
    Inventors: Roden R. Topacio, Yip Seng Low, Liane Martinez, Andrew K.W. Leung, Xiao Ling Shi