Patents by Inventor Andrew Kao

Andrew Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wireless communication technology, apparatuses, and methods
    Patent number: 11955732
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Systems and methods for serial flow emulsion processes
    Patent number: 11931736
    Abstract: Disclosed herein are systems and methods for serial flow emulsion processes. Systems and methods as described herein result in reduced cross-contamination.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: March 19, 2024
    Assignee: DROPWORKS, INC.
    Inventors: Christopher Michael Perkins, Matthew Ryan Dunn, Andrew Carl Larsen, Donna Kelley, Michael Barich, Kristopher Holub, Pin Kao
  • High density interconnect system having rapid fabrication cycle
    Patent number: 7884634
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: February 8, 2011
    Assignee: Verigy (Singapore) Pte, Ltd
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • High density interconnect system having rapid fabrication cycle
    Patent number: 7872482
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 18, 2011
    Assignee: Verigy (Singapore) Pte. Ltd
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • Systems and Methods to Use Rules and Constraints for Service Consolidation
    Publication number: 20100191572
    Abstract: Systems and methods to consolidate user preferences for a service and make suggestions for options related to the service. In one aspect, a computer-implemented method includes: storing preferences of a plurality of users for a service; storing past options that have been previously selected for the service; in response to a request for the service for a subset of the users, combining the preferences of the subset of the users to generate a preference set for the subset of the users, based on a set of predetermined rules, using a computer; and selecting an option based on the preference set generated for the subset of users and the past options that have been previously selected for the service, using the computer.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Applicant: REARDEN COMMERCE, INC.
    Inventors: Patrick NEWMAN, Andrew KAO, Aaron MUNTER
  • High Density Interconnect System Having Rapid Fabrication Cycle
    Publication number: 20090153165
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: January 15, 2009
    Publication date: June 18, 2009
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • HIGH DENSITY INTERCONNECT SYSTEM HAVING RAPID FABRICATION CYCLE
    Publication number: 20080246500
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: September 19, 2007
    Publication date: October 9, 2008
    Inventors: Fu Chiung CHONG, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • High density interconnect system having rapid fabrication cycle
    Patent number: 7382142
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 3, 2008
    Assignee: NanoNexus, Inc.
    Inventors: Fu Chiung Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank John Swiatowiec, Zhaohui Shan
  • High density interconnect system having rapid fabrication cycle
    Publication number: 20050275418
    Abstract: An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 15, 2005
    Inventors: Fu Chong, Andrew Kao, Douglas McKay, Anna Litza, Douglas Modlin, Sammy Mok, Nitin Parekh, Frank Swiatowiec, Zhaohui Shan
  • Method for magneto-resistive head electrostatic popping detection
    Patent number: 6556006
    Abstract: A method and system for detecting electrostatic noise in a magneto-resistive head which may be caused by a plurality of conditions manifesting in the frequency domain as either an amplitude spike or an unstable baseline. In one embodiment, the signals generated by the head when reading a DC-erased track are compared. When viewed in the frequency domain the spectrum gap between the signals is used to determine if the head being tested suffers from defects causing an unstable baseline or from defects causing an amplitude spike.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: April 29, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhaohui Li, Andrew Kao, Keung Youn Cho