Patents by Inventor Andrew M. Fuller
Andrew M. Fuller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960344Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: GrantFiled: December 30, 2022Date of Patent: April 16, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20230244293Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: ApplicationFiled: December 30, 2022Publication date: August 3, 2023Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 11677391Abstract: A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.Type: GrantFiled: January 26, 2022Date of Patent: June 13, 2023Assignee: Rambus Inc.Inventors: Robert E. Palmer, Andrew M. Fuller, William F. Stonecypher
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Patent number: 11556164Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: GrantFiled: December 10, 2020Date of Patent: January 17, 2023Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20210232203Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: ApplicationFiled: December 10, 2020Publication date: July 29, 2021Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 10901485Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: GrantFiled: May 21, 2019Date of Patent: January 26, 2021Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20200012332Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: ApplicationFiled: May 21, 2019Publication date: January 9, 2020Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 10331193Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: GrantFiled: August 21, 2017Date of Patent: June 25, 2019Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20180067538Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: ApplicationFiled: August 21, 2017Publication date: March 8, 2018Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 9753521Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.Type: GrantFiled: November 24, 2015Date of Patent: September 5, 2017Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 9419598Abstract: A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.Type: GrantFiled: November 12, 2014Date of Patent: August 16, 2016Assignee: Rambus Inc.Inventors: Robert E. Palmer, Michael D. Bucher, Andrew M. Fuller
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Publication number: 20160147281Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.Type: ApplicationFiled: November 24, 2015Publication date: May 26, 2016Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 9229523Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: GrantFiled: April 23, 2015Date of Patent: January 5, 2016Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20150227188Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.Type: ApplicationFiled: April 23, 2015Publication date: August 13, 2015Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20150145581Abstract: A controllable delay element includes a delay element to provide a variable delay from an input signal to an output signal. The variable delay can be controlled by a digital delay input. The delay element has a delay range that is controlled in response to a delay range input. The delay range of the delay element can be calibrated to a desired range of delays in response to a relative delay between a first timing reference and a second timing reference. A common timing reference is applied to a plurality of receivers and a strobe receiver. The delay through the strobe receiver is adjusted to measure the delay mismatches between the plurality of receivers. The mismatches are used to select a value for the delay through the strobe receiver.Type: ApplicationFiled: November 12, 2014Publication date: May 28, 2015Inventors: Robert E. Palmer, Michael D. Bucher, Andrew M. Fuller
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Patent number: 9043633Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.Type: GrantFiled: November 18, 2014Date of Patent: May 26, 2015Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Publication number: 20150074437Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.Type: ApplicationFiled: November 18, 2014Publication date: March 12, 2015Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 8918669Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.Type: GrantFiled: July 9, 2009Date of Patent: December 23, 2014Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 8918667Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.Type: GrantFiled: July 9, 2009Date of Patent: December 23, 2014Assignee: Rambus Inc.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller
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Patent number: 8509094Abstract: Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.Type: GrantFiled: December 2, 2008Date of Patent: August 13, 2013Assignee: Rambus Inc.Inventors: Andrew M. Fuller, John W. Poulton