Patents by Inventor Andrew M. Hawryluk

Andrew M. Hawryluk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9613815
    Abstract: High-efficiency line-forming optical systems and methods for defect annealing and dopant activation are disclosed. The system includes a CO2-based line-forming system configured to form at a wafer surface a first line image having between 2000 W and 3000 W of optical power. The line image is scanned over the wafer surface to locally raise the temperature up to a defect anneal temperature. The system can include a visible-wavelength diode-based line-forming system that forms a second line image that can scan with the first line image to locally raise the wafer surface temperature from the defect anneal temperature to a spike anneal temperature. Use of the visible wavelength for the spike annealing reduces adverse pattern effects and improves temperature uniformity and thus annealing uniformity.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Publication number: 20170088952
    Abstract: ALD systems and methods having high throughput are disclosed. The ALD systems and methods employ a process chamber that has multiple chamber sections defined by interior chamber dividers. The wafers to be processed are supported on a platen that rotates beneath a process chamber housing with a small gap therebetween so that the wafers are moved between the chamber sections. The multiple chamber sections are pneumatically partitioned by the dividers and by pneumatic valves operably disposed therein and in pneumatic communication with the platen surface through the gap. Some chamber sections are used to perform an ALD process using process gasses, while other chamber sections are transition sections that include a purge gas. Some chamber sections can be employed to perform a laser process or a plasma process on the wafers passing therethrough.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 30, 2017
    Applicant: Ultratech, Inc.
    Inventor: Andrew M. Hawryluk
  • Publication number: 20170062191
    Abstract: Systems and methods for coating particles using PE-ALD and a rotary reactor tube are disclosed. The reactor tube is part of a reactor tube assembly that can rotate and move axially so that it is operably disposed relative to a plasma-generating device. The plasma-generating device has an active state that generates a plasma from a precursor gas and an inactive state that passes the precursor gas without forming a plasma. The reactor tube resides in a chamber that has an open position for accessing the reactor tube and a closed position that supports a vacuum. An output end of the plasma-generating device resides immediately adjacent or within an input section of the reactor tube. This configuration avoids the need for an active portion of the plasma-generating device residing adjacent an outer surface of the reactor tube.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 2, 2017
    Applicant: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
  • Patent number: 9558973
    Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: January 31, 2017
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Serguel Anikitchev
  • Patent number: 9490128
    Abstract: Methods of annealing a thin semiconductor wafer are disclosed. The methods allow for high-temperature annealing of one side of a thin semiconductor wafer without damaging or overheating heat-sensitive electronic device features that are either on the other side of the wafer or embedded within the wafer. The annealing is performed at a temperature below the melting point of the wafer so that no significant dopant redistribution occurs during the annealing process. The methods can be applied to activating dopants or to forming ohmic contacts.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: November 8, 2016
    Assignee: Ultratech, Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk, Xiaoru Wang, Xiaohua Shen
  • Patent number: 9436103
    Abstract: A Wynne-Dyson projection lens for use in an ultraviolet optical lithography system is disclosed, wherein the projection lens is configured to have reduced susceptibility to damage from ultraviolet radiation. The projection lens utilizes lens elements that are made of optical glasses that are resistant to damage from ultraviolet radiation, but that also provide sufficient degrees of freedom to correct aberrations. The glass types used for the lens elements are selected from the group of optical glasses consisting of: fused silica, S-FPL51Y, S-FSL5Y, BSM51Y and BAL15Y.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: September 6, 2016
    Assignee: Ultratech, Inc.
    Inventors: Peiqian Zhao, Emily M. True, Raymond Ellis, Andrew M. Hawryluk
  • Publication number: 20160240440
    Abstract: Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with each other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes.
    Type: Application
    Filed: April 28, 2016
    Publication date: August 18, 2016
    Applicant: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Yun Wang, Andrew M. Hawryluk
  • Publication number: 20160240407
    Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.
    Type: Application
    Filed: September 18, 2014
    Publication date: August 18, 2016
    Applicant: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Patent number: 9401278
    Abstract: Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate. The image may be scanned across the surface to heat at least a portion of the substrate surface to achieve a desired temperature within a predetermined dwell time. Such processing may achieve a high efficiency due to the large proportion of energy contained in the uniform portion of the beam.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: July 26, 2016
    Assignee: Ultratech, Inc.
    Inventors: Andrew M Hawryluk, Boris Grek, David A Markle
  • Publication number: 20160203972
    Abstract: Atomic Layer Deposition (ALD) is used for heteroepitaxial film growth at reaction temperatures ranging from 80-400° C. The substrate and film materials are preferably selected to take advantage of Domain Matched Epitaxy (DME). A laser annealing system is used to thermally anneal deposition layers after deposition by ALD. In preferred embodiments a silicon substrate is overlaid with an AIN nucleation layer and laser annealed. Thereafter a GaN device layers is applied over the AIN layer by an ALD process and then laser annealed. In a further example embodiment a transition layer is applied between the GaN device layer and the AIN nucleation layer. The transition layer comprises one or more different transition material layers each comprising a AlxGa1-x compound wherein the composition of the transition layer is continuously varied from AIN to GaN.
    Type: Application
    Filed: September 17, 2014
    Publication date: July 14, 2016
    Applicant: Ultratech, Inc.
    Inventors: Ganesh Sundaram, Andrew M. Hawryluk, Daniel Stearns
  • Publication number: 20160181120
    Abstract: Laser annealing systems and methods with ultra-short dwell times are disclosed. The method includes locally pre-heating the wafer with a pre-heat line image and then rapidly scanning an annealing image relative to the pre-heat line image to define a scanning overlap region that has a dwell time is in the range from 10 ns to 500 ns. These ultra-short dwell times are useful for performing surface or subsurface melt annealing of product wafers because they prevent the device structures from reflowing.
    Type: Application
    Filed: November 16, 2015
    Publication date: June 23, 2016
    Applicant: ULTRATECH, INC.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Publication number: 20160155629
    Abstract: Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550° C. and preferable below 350° C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500° C. for less than 12 msec.
    Type: Application
    Filed: June 25, 2014
    Publication date: June 2, 2016
    Applicant: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Ganesh Sundaram, Ritwik Bhatia
  • Publication number: 20160148810
    Abstract: High-efficiency line-forming optical systems and methods for defect annealing and dopant activation are disclosed. The system includes a CO2-based line-forming system configured to form at a wafer surface a first line image having between 2000 W and 3000 W of optical power. The line image is scanned over the wafer surface to locally raise the temperature up to a defect anneal temperature. The system can include a visible-wavelength diode-based line-forming system that forms a second line image that can scan with the first line image to locally raise the wafer surface temperature from the defect anneal temperature to a spike anneal temperature. Use of the visible wavelength for the spike annealing reduces adverse pattern effects and improves temperature uniformity and thus annealing uniformity.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 26, 2016
    Applicant: ULTRATECH, INC.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Patent number: 9341951
    Abstract: A Wynn-Dyson imaging system with reduced thermal distortion is disclosed, wherein the reticle and wafer prisms are made of glass material having a coefficient of thermal expansion of no greater than about 100 ppb/° C. The system also includes a first IR-blocking window disposed between the reticle and the reticle prism, and a second matching window disposed between the wafer and the wafer prism to maintain imaging symmetry. The IR-blocking window substantially blocks convective and radiative heat from reaching the reticle prism, thereby reducing the amount of thermally induced image distortion in the reticle image formed on the wafer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 17, 2016
    Assignee: Ultratech, Inc.
    Inventor: Andrew M. Hawryluk
  • Patent number: 9302348
    Abstract: Systems and methods for performing ultrafast laser annealing in a manner that reduces pattern density effects in integrated circuit manufacturing are disclosed. The method includes scanning at least one first laser beam over the patterned surface of a substrate. The at least one first laser beam is configured to heat the patterned surface to a non-melt temperature Tnonmelt that is within about 400° C. of the melt temperature Tmelt. The method also includes scanning at least one second laser beam over the patterned surface and relative to the first laser beam. The at least one second laser beam is pulsed and is configured to heat the patterned surface from the non-melt temperature provided by the at least one first laser beam up to the melt temperature.
    Type: Grant
    Filed: October 6, 2012
    Date of Patent: April 5, 2016
    Assignee: Ultratech Inc.
    Inventors: Yun Wang, Andrew M. Hawryluk
  • Publication number: 20160086832
    Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 24, 2016
    Applicant: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Patent number: 9266437
    Abstract: A betavoltaic power source for transportation devices and applications is disclosed, wherein the device having a stacked configuration of isotope layers and energy conversion layers. The isotope layers have a half-life of between about 0.5 years and about 5 years and generate radiation with energy in the range from about 15 keV to about 200 keV. The betavoltaic power source is configured to provide sufficient power to operate the transportation device over its useful lifetime.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: February 23, 2016
    Assignee: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
  • Publication number: 20150331326
    Abstract: A Wynne-Dyson projection lens for use in an ultraviolet optical lithography system is disclosed, wherein the projection lens is configured to have reduced susceptibility to damage from ultraviolet radiation. The projection lens utilizes lens elements that are made of optical glasses that are resistant to damage from ultraviolet radiation, but that also provide sufficient degrees of freedom to correct aberrations. The glass types used for the lens elements are selected from the group of optical glasses consisting of: fused silica, S-FPL51Y, S-FSL5Y, BSM51Y and BAL15Y.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 19, 2015
    Applicant: Ultratech, Inc.
    Inventors: Peiqian Zhao, Emily M. True, Raymond Ellis, Andrew M. Hawryluk
  • Patent number: 9190570
    Abstract: The disclosure is directed to laser annealing of GaN light-emitting diodes (LEDs) with reduced pattern effects. A method includes forming elongate conductive structures atop either an n-GaN layer or a p-GaN layer of a GaN LED structure, the elongate conductive structures having long and short dimensions, and being spaced apart and substantially aligned in the long dimensions. The method also includes generating a P-polarized anneal laser beam that has an anneal wavelength that is greater than the short dimension. The method also includes irradiating either the n-GaN layer or the p-GaN layer of the GaN LED structure through the conductive structures with the P-polarized anneal laser beam, including directing the anneal laser beam relative to the conductive structures so that the polarization direction is perpendicular to the long dimension of the conductive structures.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 17, 2015
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Yun Wang
  • Publication number: 20150090180
    Abstract: A method of epitaxially growing a final film using a crystalline substrate wherein the final film cannot be grown directly on the substrate surface is disclosed. The method includes forming a transition layer on the upper surface of the substrate. The transition layer has a lattice spacing that varies between its lower and upper surfaces. The lattice spacing at the lower surface matches the lattice spacing of the substrate to within a first lattice mismatch of 7%. The lattice spacing at the upper surface matches the lattice spacing of the final film to within a second lattice mismatch of 7%. The method also includes forming the final film on the upper surface of the transition layer.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Daniel Stearns