Abstract: A variable trip limit transient blocking unit (TBU) is provided. The variable trip limit transient blocking unit circuit includes a transient blocking unit and a low-pass filter, such as an RC circuit having an RC time constant. The RC circuit is disposed to approximate an integrator operating over periods of time that are short compared to the RC time constant. The RC circuit integrates a signal representing an approximated current flowing through the transient blocking unit and triggers a disconnect threshold in the transient blocking unit when a voltage stored across a capacitor of the RC circuit reaches a predefined limit.

Abstract: Various techniques directed to the digital control of a switching regulator are disclosed. In one aspect, a power supply regulator includes a compare circuit to be coupled to receive a feedback signal representative of an output level of a power supply. This causes a feedback state signal to be generated having a first feedback state that represents an output level of the power supply that is above a threshold level and a second feedback state that represents an output level of the power supply that is below the threshold level. An adjustment circuit is coupled to the compare circuit to adjust the feedback state signal in response to at least one of adjusting the threshold level or adjusting the feedback signal. The adjustment to the feedback state signal tends to cause the feedback state signal to revert from a state at the time of adjustment to a state immediately preceding the adjustment.

Abstract: Various techniques directed to the digital control of a switching regulator are disclosed. In one aspect, a method for regulating an output level at a power converter output includes receiving a feedback signal representative of the output level at the power converter output. In response to a state of the power converter, at least one of the feedback signal or a threshold level is adjusted. A feedback state signal is generated having a first feedback state that represents that the output level is above the threshold level and a second feedback state that represents that the output level is below the threshold level. A duty cycle signal that cycles is generated. In response to a control signal, energy from a power converter input is enabled or disabled to flow to the power converter output. The control signal is responsive to the duty cycle signal and to a change between the first and second feedback states. The control signal is also responsive to a change between the first and second feedback states.

Abstract: Techniques are disclosed to limit the current in a switch of a switching power supply. An example switching regulator circuit includes a power switch to be coupled to an energy transfer element of a power supply. A controller to generate a drive signal is coupled to be received by the power switch to control the switching of the power switch. A short on time detector is included in the controller. The short on time detector is to detect an occurrence of a threshold number of one or more consecutive short on times of the switch. A frequency adjuster is also included in the controller and coupled to the short on time detector. The frequency adjuster is to adjust an oscillating frequency of an oscillator included in the controller in response to the short on time detector.

Abstract: A system for regulating beam current in a cathode ray tube. The system includes test signal timing and pulse generation logic for outputting test signals operable to stimulate a cathode ray tube at two voltage levels. The system further includes a circuit that inputs the test signal timing and determines correction signals based on signals derived from the cathode in response to stimulating the cathode ray tube at the two voltage levels. The correction signals may include a gain correction signal, a bias correction signal or both. The gain correction signal modifies a signal output to a gain driver that may be AC coupled to the cathode. The bias correction signal output to a clamping circuit coupled to the cathode.

Abstract: A circuit for regulating a signal, such as a cathode current. The circuit has an input stage for inputting a signal and for producing a sense signal based thereon. The circuit may input timing signals and have a first stage for comparing a first reference signal with the sense signal when a first timing signal indicates and for outputting a first correction signal based on the comparison. The circuit may have a second stage for comparing a second reference signal with the sense signal when a second timing signal indicates and for outputting a second correction signal based on the comparison. The circuit may further have elements for measuring a leakage signal in the input signal during a third time interval. In this embodiment, the first and second stages are further for subtracting the leakage signal from the sense signal prior to the comparisons.

Abstract: A multiplexed video signal interface in accordance with the present invention provides a multiplexed component video signal in which, in addition to the component video signals with OSD data and user-controllable contrast and video gain, includes control signal components for image brightness and CRT bias along with the ability to individually control such control signal components. This advantageously minimizes the complexity of the necessary signal interfaces and allows for greater integration of circuit functions, thereby significantly reducing circuit complexity, size and costs.

Abstract: A system, method, and apparatus for displaying a character on a television or monitor screen are presented. The contents from a first memory location are fetched to determine the character and character attributes to be displayed. A graphical representation for the character to be displayed is then retrieved and overwritten based on the character attribute information of the character and a second character, such as an adjacent character.

Abstract: A character line address counter clock signal generator for generating a character line address counter clock signal for an on screen display (OSD) circuit used to selectively display a character image within an on screen display contained within a displayed screen image. The character image displayed within the OSD is maintained at a substantially constant image height regardless of the number of image lines contained within the overall displayed screen image. The character image lines for a base character image are displayed in accordance with a predetermined repetition sequence without requiring phase lock loop to generate a reduced character line address clock or requiring arithmetic computation to calculate each character line address.

Abstract: A vertical blanking amplifier and bias clamp boost supply in accordance with the present invention uses the amplified vertical blanking signal to generate the boosted high voltage needed for powering the bias clamp circuits. A latch circuit is used to effectively lengthen the duration of the first vertical blanking pulse so as to ensure that the boosted power supply voltage is generated in the short time interval of one or two vertical scan intervals.

Abstract: An analog amplifier with a monotonic transfer function converts an incoming analog control voltage into multiple continuously variable discrete analog control voltages which are then used to control the respective gate biases of multiple MOS transistors. The MOS transistors are each connected in series with respective associated resistors and in a laddered parallel configuration with other serial transistor-resistor pairs. This creates a variable impedance circuit which, in accordance with the continuously variable discrete analog control voltages, exhibits a corresponding continuously variable circuit impedance in the form of a continuously variable resistance. This variable resistance forms part of the feedback circuit for controlling the gain of a noninverting operational amplifier circuit. This causes the ratio of the analog output and input signals of such operational amplifier circuit to define a monotonic transfer function.

Abstract: A high gain, current driven amplifier uses an emitter follower circuit with another emitter follower circuit connected in a feedback configuration to drive a common base amplifier circuit in place of a conventional cascode amplifier configuration to achieve a high frequency response with adequate signal gain. A differential input signal can be used, thereby minimizing input DC offsets, drift and noise, by using a differential amplifier to convert a differential input signal voltage to the input signal current for driving the emitter follower circuits. The current gain is determined by a ratio of the resistances in the emitter circuits of the emitter follower circuits. In one embodiment, the currents formed in the emitter follower circuits are summed at the input to the common base amplifier circuit, while in another embodiment, such currents are summed at the output of the common base amplifier circuit.

Abstract: A digitally controlled signal attenuator circuit which allows an incoming DC-clamped signal to be selectively attenuated using a set of digital control signals while maintaining its DC clamping. Multiple stages of such a circuit can be cascaded to provide for multiple forms of signal attenuation without affecting the clamping. Preferred forms of the attenuator circuit use pass transistors and transmission gates as switches for selectively altering the resistance values of resistive circuits connected in shunt to and in series with the signal being attenuated. In the case of where the subject signal is a variable DC signal such a brightness control voltage, such circuit configurations also allow the output signal voltage range to include values which are more negative than the DC clamp voltage as well as more positive.