Abstract: A system for flight control in electric aircraft includes a flight controller configured to provide an initial vehicle torque signal including a plurality of attitude commands. The system includes a mixer configured to receive the initial vehicle torque signal and a vehicle torque limit, receive prioritization data including a prioritization datum corresponding to each of the plurality of attitude command, determine a plurality of modified attitude commands as a function of the vehicle torque limit, the attitude commands, and the prioritization data, generate, as a function of modified attitude commands, an output torque command including the initial vehicle torque signal adjusted as a function of the vehicle torque limit, generate, as a function of the output torque command, a remaining vehicle torque. The system includes a display, wherein the display is configured to present, to a user, the remaining vehicle torque and the output torque command.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are transferred to faster intermediate memory between a requester and the slower main memory. The selected data items are retrieved from the slower main memory into a prefetch read buffer as an intermediate memory prior to any request from the requester for the particular selected and prefetched data. The address and size of the prefetched data is derived from the history, pattern, or trajectory of prior memory reads.

Abstract: Provided are a method, system, and program for processing operations in a system including a bus, a target device and devices capable of accessing the target device over the bus. The target device receives a transaction request from one of the devices over the bus and determines whether a delayed read request is pending after receiving the transaction request. The target device issues a command to disconnect the device initiating the transaction request from the bus. The device initiating the transaction request is allowed to reconnect to the bus and complete the transaction request after the delayed read request is completed.

Abstract: Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are transferred to faster intermediate memory between a requester and the slower main memory. The selected data items are retrieved from the slower main memory into a prefetch read buffer as an intermediate memory prior to any request from the requester for the particular selected and prefetched data. The address and size of the prefetched data is derived from the history, pattern, or trajectory of prior memory reads.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0 is disclosed. The PCI-to-PCI bridge function is implemented in PCI devices using the standard Type 0 PCI Configuration Header that supports up to six Base Address Registers. Having the PCI-to-PCI bridge function integrated with other PCI device functions has the advantage of reducing valuable card real estate and power consumption.

Abstract: An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.

Abstract: Provided are a method, system, and program for performing initialization operations in a system including a bus, bus interface and at least one bus device communicating on the bus. The bus interface includes memory capable of being accessed over the bus by the at least one bus device. All bus devices capable of communicating on the bus are detected and each detected bus device and bus interface is configured with base addresses that enable transmission of Input/Output (I/O) requests over the bus to the memory in the bus interface and memory in any bus device including memory accessible over the bus. Testing is performed on the base addresses of the memory in each bus device including memory accessible over the bus by issuing I/O requests to the base addresses of the memory in each bus device. Memory in the bus interface is tested by issuing I/O requests to the base addresses of the memory in the bus interface over the bus.

Abstract: Provided are a method, system, and program for processing operations in a system including a bus, a target device and devices capable of accessing the target device over the bus. The target device receives a transaction request from one of the devices over the bus and determines whether a delayed read request is pending after receiving the transaction request. The target device issues a command to disconnect the device initiating the transaction request from the bus. The device initiating the transaction request is allowed to reconnect to the bus and complete the transaction request after the delayed read request is completed.

Abstract: A method and apparatus embedding PCI-to-PCI bridge functions in PCI devices using PCI configuration header type 0 is disclosed. The PCI-to-PCI bridge function is implemented in PCI devices using the standard Type 0 PCI Configuration Header that supports up to six Base Address Registers. Having the PCI-to-PCI bridge function integrated with other PCI device functions has the advantage of reducing valuable card real estate and power consumption.

Abstract: Provided are a method, system, and program for performing initialization operations in a system including a bus, bus interface and at least one bus device communicating on the bus. The bus interface includes memory capable of being accessed over the bus by the at least one bus device. All bus devices capable of communicating on the bus are detected and each detected bus device and bus interface is configured with base addresses that enable transmission of Input/Output (I/O) requests over the bus to the memory in the bus interface and memory in any bus device including memory accessible over the bus. Testing is performed on the base addresses of the memory in each bus device including memory accessible over the bus by issuing I/O requests to the base addresses of the memory in each bus device. Memory in the bus interface is tested by issuing I/O requests to the base addresses of the memory in the bus interface over the bus.

Abstract: A global label (path identifier) is stored at compile time which computes a check marker along one permissible execution path of execution of a microinstruction sequence. The remaining execution paths are embedded with scalars and skip microinstructions so that execution along any conditional branch path will always yield the same global label (path identifier). Microcode sequence errors are determined at the completion of each microprogram node execution by comparing a path identifier generated at runtime with the global label stored earlier.