Patents by Inventor Andrew Parke
Andrew Parke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854600Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.Type: GrantFiled: September 20, 2019Date of Patent: December 1, 2020Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
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Publication number: 20200013775Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: JUSTIN ANDREW PARKE, ERIC J. STEWART, ROBERT S. HOWELL, HOWELL GEORGE HENRY, BETTINA NECHAY, HARLAN CARL CRAMER, MATTHEW RUSSELL KING, SHALINI GUPTA, RONALD G. FREITAG, KAREN MARIE RENALDO
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Patent number: 10468406Abstract: A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.Type: GrantFiled: October 8, 2014Date of Patent: November 5, 2019Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
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Patent number: 10084075Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: GrantFiled: June 15, 2017Date of Patent: September 25, 2018Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Shalini Gupta, Matthew Russell King, Eric J. Stewart, Robert S. Howell, Justin Andrew Parke, Harlan Carl Cramer, Howell George Henry, Ronald G. Freitag, Karen Marie Renaldo
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Publication number: 20170288045Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, SHALINI GUPTA, MATTHEW RUSSELL KING, ERIC J. STEWART, ROBERT S. HOWELL, JUSTIN ANDREW PARKE, HARLAN CARL CRAMER, HOWELL GEORGE HENRY, RONALD G. FREITAG, KAREN MARIE RENALDO
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Patent number: 9773897Abstract: A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.Type: GrantFiled: April 1, 2015Date of Patent: September 26, 2017Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Robert S. Howell, Eric J. Stewart, Howell George Henry, Justin Andrew Parke, Ronald G. Freitag
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Patent number: 9755021Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.Type: GrantFiled: June 17, 2016Date of Patent: September 5, 2017Assignee: Northrop Grumman Systems CorporationInventors: Karen M. Renaldo, Eric J. Stewart, Robert S. Howell, Howell George Henry, Harlan Carl Cramer, Justin Andrew Parke, Matthew Russell King
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Patent number: 9711615Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: GrantFiled: July 28, 2016Date of Patent: July 18, 2017Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Shalini Gupta, Matthew Russell King, Eric J. Stewart, Robert S. Howell, Justin Andrew Parke, Harlan Carl Cramer, Howell George Henry, Ronald G. Freitag, Karen Marie Renaldo
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Patent number: 9593029Abstract: A system and method for providing mobile or temporary water treatment involving ion exchange resins includes a service center, one or more treatment vehicles, a resin transfer hub and one or more resin transport vehicles. The service center can be used to regenerate one or more types of ion exchange resins. The treatment vehicle carries water treatment equipment including a tank holding ion exchange resin. The resin transfer hub facilitates moving resin between a treatment vehicle and a resin transport vehicle. The resin transport vehicle is adapted for carrying resin by one or more of land, sea and air between the resin forwarding center and the service center. In operation, a treatment vehicle brings resin requiring regeneration to the resin transfer hub, where it is emptied and then re-filled with regenerated resin. Resin requiring regeneration is transferred to a resin transport vehicle for transport to the service center.Type: GrantFiled: March 12, 2015Date of Patent: March 14, 2017Assignee: GENERAL ELECTRIC COMPANYInventor: Andrew Parke
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Publication number: 20160336425Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, SHALINI GUPTA, MATTHEW RUSSELL KING, ERIC J. STEWART, ROBERT S. HOWELL, JUSTIN ANDREW PARKE, HARLAN CARL CRAMER, HOWELL GEORGE HENRY, RONALD G. FREITAG, KAREN MARIE RENALDO
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Publication number: 20160315152Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterorstructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.Type: ApplicationFiled: June 17, 2016Publication date: October 27, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: KAREN M. RENALDO, ERIC J. STEWART, ROBERT S. HOWELL, HOWELL GEORGE HENRY, HARLAN CARL CRAMER, JUSTIN ANDREW PARKE, MATTHEW RUSSELL KING
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Patent number: 9472634Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.Type: GrantFiled: March 9, 2016Date of Patent: October 18, 2016Assignee: Northrop Grumman Systems CorporationInventors: Eric J Stewart, Howell George Henry, Robert S. Howell, Matthew Russell King, Justin Andrew Parke, Bettina Nechay, Harlan Carl Cramer, Ronald G Freitag, Karen Marie Renaldo
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Patent number: 9466679Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.Type: GrantFiled: August 13, 2014Date of Patent: October 11, 2016Assignee: Northrop Grumman Systems CorporationInventors: Eric J. Stewart, Howell George Henry, Robert S. Howell, Matthew Russell King, Justin Andrew Parke, Bettina Nechay, Harlan Carl Cramer, Karen Marie Renaldo, Ronald G. Freitag
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Publication number: 20160293713Abstract: A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure comprises a multichannel ridge having sides that extend to the base structure. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge. A three-sided gate configuration is provided that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. The three-sided gate configuration is configured to re-distribute peak electric fields along the three-sided gate configuration to facilitate the increase in breakdown voltage of the transistor device.Type: ApplicationFiled: April 1, 2015Publication date: October 6, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, Robert S. Howell, Eric J. Stewart, Howell George Henry, Justin Andrew Parke, Ronald G. Freitag
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Patent number: 9419120Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: GrantFiled: November 5, 2014Date of Patent: August 16, 2016Assignee: Northrop Grumman Systems CorporationInventors: Bettina A. Nechay, Shalini Gupta, Matthew Russell King, Eric J. Stewart, Robert S. Howell, Justin Andrew Parke, Harlan Carl Cramer, Howell George Henry, Ronald G. Freitag, Karen Marie Renaldo
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Patent number: 9385224Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.Type: GrantFiled: August 13, 2014Date of Patent: July 5, 2016Assignee: Northrop Grumman Systems CorporationInventors: Karen M. Renaldo, Eric J. Stewart, Robert S. Howell, Howell George Henry, Harlan Carl Cramer, Justin Andrew Parke, Matthew Russell King
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Publication number: 20160190267Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: ERIC J. STEWART, HOWELL GEORGE HENRY, ROBERT S. HOWELL, MATTHEW RUSSELL KING, JUSTIN ANDREW PARKE, BETTINA NECHAY, HARLAN CARL CRAMER, RONALD G. FREITAG, KAREN MARIE RENALDO
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Publication number: 20160126340Abstract: A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.Type: ApplicationFiled: November 5, 2014Publication date: May 5, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: BETTINA A. NECHAY, SHALINI GUPTA, MATTHEW RUSSELL KING, ERIC J. STEWART, ROBERT S. HOWELL, JUSTIN ANDREW PARKE, HARLAN CARL CRAMER, HOWELL GEORGE HENRY, RONALD G. FREITAG, KAREN MARIE RENALDO
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Publication number: 20160104703Abstract: A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: JUSTIN ANDREW PARKE, ERIC J. STEWART, ROBERT S. HOWELL, HOWELL GEORGE HENRY, BETTINA NECHAY, HARLAN CARL CRAMER, MATTHEW RUSSELL KING, SHALINI GUPTA, RONALD G. FREITAG, KAREN MARIE RENALDO
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Publication number: 20160049504Abstract: An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device.Type: ApplicationFiled: August 13, 2014Publication date: February 18, 2016Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: KAREN M. RENALDO, ERIC J. STEWART, ROBERT S. HOWELL, HOWELL GEORGE HENRY, HARLAN CARL CRAMER, JUSTIN ANDREW PARKE, MATTHEW RUSSELL KING