Patents by Inventor Andrew R. Bicksler
Andrew R. Bicksler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11424256Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: GrantFiled: October 24, 2019Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Publication number: 20200058662Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: ApplicationFiled: October 24, 2019Publication date: February 20, 2020Applicant: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Patent number: 10497707Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: GrantFiled: February 22, 2017Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Publication number: 20170162589Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Patent number: 9613978Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: GrantFiled: November 23, 2015Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Publication number: 20160079274Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: ApplicationFiled: November 23, 2015Publication date: March 17, 2016Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Patent number: 9219132Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: GrantFiled: September 19, 2014Date of Patent: December 22, 2015Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Publication number: 20150044834Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: ApplicationFiled: September 19, 2014Publication date: February 12, 2015Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Patent number: 8853769Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: GrantFiled: January 10, 2013Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Publication number: 20140191340Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.Type: ApplicationFiled: January 10, 2013Publication date: July 10, 2014Applicant: Micron Technology, Inc.Inventors: Deepak Thimmegowda, Andrew R. Bicksler, Roland Awusie
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Patent number: 7358139Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: GrantFiled: July 20, 2006Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Patent number: 7271064Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: GrantFiled: August 24, 2005Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Patent number: 7112491Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: GrantFiled: April 29, 2004Date of Patent: September 26, 2006Assignee: Micron Technology, Inc.Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Publication number: 20050282339Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: ApplicationFiled: August 24, 2005Publication date: December 22, 2005Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Patent number: 6830975Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: GrantFiled: January 31, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Publication number: 20040203209Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: ApplicationFiled: April 29, 2004Publication date: October 14, 2004Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Patent number: 6798699Abstract: A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.Type: GrantFiled: February 24, 2003Date of Patent: September 28, 2004Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Chun Chen, Paul Rudeck, Andrew R. Bicksler
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Publication number: 20030143814Abstract: The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising a conductive metal or metal compound received over conductively doped semiconductive material includes forming transistor gate semiconductive material into a gate line over a semiconductive material channel region. The gate line includes semiconductive material sidewalls. The semiconductive material sidewalls of the gate line are oxidized. After the oxidizing, at least one of a conductive metal or metal compound is formed in electrical connection with the transistor gate semiconductive material to comprise a substantially coextensive elongated portion of a final construction of the gate line of the field effect transistor being formed.Type: ApplicationFiled: January 31, 2002Publication date: July 31, 2003Inventors: Andrew R. Bicksler, Sukesh Sandhu
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Publication number: 20030128591Abstract: A non-volatile memory device for erasing a block of stack-gate single transistor flash memory cells performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array to fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block, bringing a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunneling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.Type: ApplicationFiled: February 24, 2003Publication date: July 10, 2003Applicant: Micron Technology, Inc.Inventors: Andrei Mihnea, Chun Chen, Paul Rudeck, Andrew R. Bicksler
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Patent number: 6563741Abstract: A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential.Type: GrantFiled: January 30, 2001Date of Patent: May 13, 2003Assignee: Micron Technology, Inc.Inventors: Andrei Mihnea, Chun Chen, Paul Rudeck, Andrew R. Bicksler