Patents by Inventor Andrew Ritenour
Andrew Ritenour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9368670Abstract: Disclosed herein are embodiments of methods for making GaAs thin films, such as photovoltaic GaAs thin films. The methods disclosed herein utilize sources, precursors, and reagents that do not produce (or require) toxic gas and that are readily available and relatively low in cost. In some embodiments, the methods are readily scalable for industrial applications and can provide GaAs thin films having properties that are at least comparable to or potentially superior to GaAs films obtained from conventional methods.Type: GrantFiled: April 21, 2015Date of Patent: June 14, 2016Assignee: University of OregonInventors: Shannon Boettcher, Andrew Ritenour, Jason Boucher, Ann Greenaway
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Publication number: 20150303347Abstract: Disclosed herein are embodiments of methods for making GaAs thin films, such as photovoltaic GaAs thin films. The methods disclosed herein utilize sources, precursors, and reagents that do not produce (or require) toxic gas and that are readily available and relatively low in cost. In some embodiments, the methods are readily scalable for industrial applications and can provide GaAs thin films having properties that are at least comparable to or potentially superior to GaAs films obtained from conventional methods.Type: ApplicationFiled: April 21, 2015Publication date: October 22, 2015Inventors: Shannon Boettcher, Andrew Ritenour, Jason Boucher, Ann Greenaway
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Patent number: 8884270Abstract: Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.Type: GrantFiled: March 30, 2012Date of Patent: November 11, 2014Assignee: Power Integrations, Inc.Inventors: Janna Casady, Jeffrey Casady, Kiran Chatty, David Sheridan, Andrew Ritenour
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Patent number: 8659057Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.Type: GrantFiled: May 20, 2011Date of Patent: February 25, 2014Assignee: Power Integrations, Inc.Inventors: Andrew Ritenour, David C. Sheridan
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Patent number: 8466017Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.Type: GrantFiled: December 8, 2010Date of Patent: June 18, 2013Assignee: Power Integrations, Inc.Inventors: David C. Sheridan, Andrew Ritenour
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Publication number: 20130011979Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: SS SC IP, LLCInventors: Andrew RITENOUR, David C. SHERIDAN
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Publication number: 20120261675Abstract: Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.Type: ApplicationFiled: March 30, 2012Publication date: October 18, 2012Applicant: SS SC IP, LLCInventors: Janna CASADY, Jeffrey CASADY, Kiran CHATTY, David SHERIDAN, Andrew RITENOUR
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Publication number: 20110291107Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.Type: ApplicationFiled: May 20, 2011Publication date: December 1, 2011Applicant: SEMISOUTH LABORATORIES, INC.Inventors: Andrew Ritenour, David C. Sheridan
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Patent number: 7994548Abstract: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.Type: GrantFiled: July 10, 2008Date of Patent: August 9, 2011Assignee: Semisouth Laboratories, Inc.Inventors: David C. Sheridan, Andrew Ritenour
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Publication number: 20110133212Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.Type: ApplicationFiled: December 8, 2010Publication date: June 9, 2011Applicant: SEMISOUTH LABORATORIES, INC.Inventors: David C. SHERIDAN, Andrew RITENOUR
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Publication number: 20090278137Abstract: Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.Type: ApplicationFiled: July 10, 2008Publication date: November 12, 2009Applicant: SemiSouth Laboratories, Inc.Inventors: David C. Sheridan, Andrew Ritenour
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Publication number: 20070069247Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: ApplicationFiled: November 16, 2006Publication date: March 29, 2007Applicant: E INK CORPORATIONInventors: Karl Amundson, Andrew Ritenour, Gregg Duthaler, Paul Drzaic, Yu Chen, Peter Kazlas
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Publication number: 20070035532Abstract: A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.Type: ApplicationFiled: July 31, 2006Publication date: February 15, 2007Applicant: E INK CORPORATIONInventors: Karl Amundson, Yu Chen, Kevin Denis, Paul Drzaic, Peter Kazlas, Andrew Ritenour
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Publication number: 20060223282Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: ApplicationFiled: June 15, 2006Publication date: October 5, 2006Applicant: E INK CORPORATIONInventors: Karl Amundson, Guy Danner, Gregg Duthaler, Peter Kazlas, Yu Chen, Kevin Denis, Nathan Kane, Andrew Ritenour
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Publication number: 20060099782Abstract: Interfaces that are portions of semiconductor structures used in integrated circuits and optoelectronic devices are described. In one instance, the semiconductor structure has an interface including a semiconductor surface, an interfacial layer including sulfur, and an electrically active layer (e.g., a dielectric or a metal). Such an interface can inhibit oxidation and improve the carrier mobility of the semiconductor structures in which such an interface is incorporated. The interfacial layer can be created by exposure of the semiconductor surface to sulfur donating compounds (e.g., H2S or SF6) and, optionally, heating.Type: ApplicationFiled: October 14, 2005Publication date: May 11, 2006Applicant: Massachusetts Institute of TechnologyInventor: Andrew Ritenour
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Publication number: 20050078099Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: ApplicationFiled: October 27, 2004Publication date: April 14, 2005Applicant: E INK CORPORATIONInventors: Karl Amundson, Andrew Ritenour, Gregg Duthaler, Paul Drzaic, Yu Chen, Peter Kazlas