Abstract: A method is provided for decompressing wide word data compressed in parallel. The method includes creating an instance of memory structure for a wide word in the wide word data, where the instance of memory structure is an inverse of a compression dictionary for the wide word; retrieving multiple compressed codes iteratively from a gap-free compressed output stream of the wide word data using the instance of memory structure, where each compressed code includes at least one character code and a reverse-pointer, and where at least one compressed code includes a multi-symbol string having a multiple character codes; forming an intermediate decompressed output stream by iteratively following the reverse-pointers for the multiple compressed codes, respectively; and forming decompressed output stream by reversing an order of the character codes in the multi-symbol string of the at least one compressed code.

Abstract: A method is provided for decompressing wide word data compressed in parallel. The method includes creating an instance of memory structure for a wide word in the wide word data, where the instance of memory structure is an inverse of a compression dictionary for the wide word; retrieving multiple compressed codes iteratively from a gap-free compressed output stream of the wide word data using the instance of memory structure, where each compressed code includes at least one character code and a reverse-pointer, and where at least one compressed code includes a multi-symbol string having a multiple character codes; forming an intermediate decompressed output stream by iteratively following the reverse-pointers for the multiple compressed codes, respectively; and forming decompressed output stream by reversing an order of the character codes in the multi-symbol string of the at least one compressed code.

Abstract: A method is provided for reducing data stored in a capture buffer of an interposer circuit during communication of the data over a data link according to a high-speed, layered packet-based protocol for analysis. The method includes performing data integrity checks of the data in real time, and omitting data integrity bits corresponding to the data integrity checks from transaction layer packets (TLPs) and data link layer packets (DLLPs) of the data when the data integrity checks indicate the data is correct; performing acknowledge and negative acknowledge (ACK/NACK) matching in real time to confirm successful delivery of the TLPs of the data using ACK/NACK packets, where the ACK/NACK packets are omitted from being stored in the capture buffer; removing and/or reducing fields in real time from the TLPs and/or the DLLPs of the data; and compressing data payloads of the TLPs and/or the DLLPs of the data in parallel.

Abstract: A method is provided for reducing data stored in a capture buffer of an interposer circuit during communication of the data over a data link according to a high-speed, layered packet-based protocol for analysis. The method includes performing data integrity checks of the data in real time, and omitting data integrity bits corresponding to the data integrity checks from transaction layer packets (TLPs) and data link layer packets (DLLPs) of the data when the data integrity checks indicate the data is correct; performing acknowledge and negative acknowledge (ACK/NACK) matching in real time to confirm successful delivery of the TLPs of the data using ACK/NACK packets, where the ACK/NACK packets are omitted from being stored in the capture buffer; removing and/or reducing fields in real time from the TLPs and/or the DLLPs of the data; and compressing data payloads of the TLPs and/or the DLLPs of the data in parallel.

Abstract: An apparatus that searches an input stream having a sequence of N-bit wide data words for a pattern using a plurality of small FSMs is disclosed. The apparatus includes a plurality of sub-word FSMs and a combiner. Each sub-word FSM has an input word size less than N-bits. Each FSM processes a corresponding segment of the N-bit words and generates a match output indicative of a possible match to the pattern when one of the input words to that FSM is received and that FSM moves to a predetermined match state. The combiner receives the match outputs from all of the sub-word FSMs and generates a pattern match output if all of the sub-word FSMs indicate a match to the pattern. The pattern is a variable pattern. In one embodiment, the FSMs are single bit FSMs.

Abstract: An apparatus and a method for using a signal analyzer are disclosed. The apparatus includes an input port having a first plurality of input channels. The input port generates a digital data stream from each of the first plurality of input channels. The apparatus also includes a trigger bank having a second plurality of trigger processors, each trigger processor receiving a digital data stream chosen from the digital data streams and generating a trigger output having one of a plurality of possible values from the digital data stream. A trigger combiner that receives each of the trigger outputs and generates a trigger signal if the combined trigger outputs satisfy a predetermined criterion. A controller copies the digital data streams to a memory and copies the trigger processor outputs to the memory in response to the trigger combiner generating the trigger signal.

Abstract: An apparatus and a method for using a signal analyzer are disclosed. The apparatus includes an input port having a first plurality of input channels. The input port generates a digital data stream from each of the first plurality of input channels. The apparatus also includes a trigger bank having a second plurality of trigger processors, each trigger processor receiving a digital data stream chosen from the digital data streams and generating a trigger output having one of a plurality of possible values from the digital data stream. A trigger combiner that receives each of the trigger outputs and generates a trigger signal if the combined trigger outputs satisfy a predetermined criterion. A controller copies the digital data streams to a memory and copies the trigger processor outputs to the memory in response to the trigger combiner generating the trigger signal.

Abstract: A method of operating a measurement instrument, such as a digital oscilloscope, includes receiving multiple analog input signals from a measurement target over respective channels, converting the analog input signal on each channel into a respective digital signal, and comparing signal values of the digital signal on each channel to at least one threshold to generate a stream of levels for each channel. The method includes combining the stream of levels for each channel into a combined stream of levels that reflects combined features of the multiple analog input signals, detecting a pattern in the combined stream of levels using a combined-feature matching procedure implemented by hardware, such as a Finite State Machine (FSM), and triggering the measurement instrument according to a result of the combined-feature matching procedure.

Abstract: A method for operating a data processing system to decode a data packet and computer readable medium that causes a data processor to perform that method when the media read by the data processing system is disclosed. The method provides a model of the possible data packet formats and an iterative process for moving through the model to decode a data packet. The model includes a plurality of nodes connected by arcs. The program iteratively examines the data packet by proceeding to a next node from a current node. The current node examines a portion of the data packet by matching each of a plurality of candidate matches to that portion of the data packet. The candidate matches include a pattern to be matched against the portion, a priority that determines the order in which the candidates matches are matched, and the identity of the next node.

Abstract: A measurement instrument receives an analog input signal from a measurement target, converts the input signal into a digital signal, scans the digital signal and comparing the scanned digital signal with a pattern signature using a flexible matching procedure implemented by hardware, and triggers the measurement instrument according to a result of the flexible matching procedure.

Abstract: An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, an FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an analog input signal. The symbols have a number of states that is less than or equal to 16. The controller causes the FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the analog signal. A portion of a digital sequence generated from the analog signal is then displayed based on the location of the pattern in the sequence of symbols.

Abstract: A method of operating a measurement instrument, such as a digital oscilloscope, includes receiving multiple analog input signals from a measurement target over respective channels, converting the analog input signal on each channel into a respective digital signal, and comparing signal values of the digital signal on each channel to at least one threshold to generate a stream of levels for each channel. The method includes combining the stream of levels for each channel into a combined stream of levels that reflects combined features of the multiple analog input signals, detecting a pattern in the combined stream of levels using a combined-feature matching procedure implemented by hardware, such as a Finite State Machine (FSM), and triggering the measurement instrument according to a result of the combined-feature matching procedure.

Abstract: A method for operating a data processing system to extract information from a record is disclosed. The method includes defining a plurality of ALTERNATIVE statements. Each ALTERNATIVE statement includes a label that identifies that ALTERNATIVE statement, a Signature that defines a test that is to be performed on a field in the data record defined by a first window, and a NEXT statement that defines a different ALTERNATIVE statement and a second window for testing by that different ALTERNATIVE statement. In one aspect of the invention, the test includes a regular expression that is to match the field. The method defines a SCHEMA statement that defines a plurality of fields within the record. One of the defined fields includes an offset defining a location in the record, a field name, and a field length. The offset and/or the field length are computed by the data processing system.

Abstract: An apparatus that searches for a pattern in a signal is disclosed. The apparatus can be used to implement a real time trigger in an instrument such as a high speed oscilloscope. The apparatus includes a symbol generator and a finite state machine (FSM). The symbol generator receives an ordered sequence of signal values and converts the ordered sequence of signal values into an ordered sequence of symbols, each symbol having a plurality of states. The FSM receives the ordered sequence of symbols and generates a match signal if the ordered sequence of symbols includes a target sequence specified by a regular expression that includes a counting limitation on one of the symbol states. The FSM includes a counting state that includes a counter that counts instances of the one of the symbol states.

Abstract: An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, an FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an analog input signal. The symbols have a number of states that is less than or equal to 16. The controller causes the FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the analog signal. A portion of a digital sequence generated from the analog signal is then displayed based on the location of the pattern in the sequence of symbols.

Abstract: An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, a multi-symbol FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an ordered sequence of digital values. The symbol generator generates one symbol corresponding to each of the digital values. The digital values have a greater number of possible values than the symbols. The controller causes the multi-symbol FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the sequence of digital values. A portion of the digital sequence is then displayed based on the location of the pattern in the sequence of symbols.

Abstract: An apparatus that can be configured for various functions such as a digital oscilloscope, logic analyzer or frequency analyzer is disclosed. The apparatus includes a symbol generator, a multi-symbol FSM, and a controller. The symbol generator generates an ordered sequence of symbols from an ordered sequence of digital values. The symbol generator generates one symbol corresponding to each of the digital values. The digital values have a greater number of possible values than the symbols. The controller causes the multi-symbol FSM to search for a pattern in the sequence of symbols that identifies a corresponding pattern in the sequence of digital values. A portion of the digital sequence is then displayed based on the location of the pattern in the sequence of symbols.

Abstract: An apparatus that searches an input stream having a sequence of N-bit wide data words for a pattern using a plurality of small FSMs is disclosed. The apparatus includes a plurality of sub-word FSMs and a combiner. Each sub-word FSM has an input word size less than N-bits. Each FSM processes a corresponding segment of the N-bit words and generates a match output indicative of a possible match to the pattern when one of the input words to that FSM is received and that FSM moves to a predetermined match state. The combiner receives the match outputs from all of the sub-word FSMs and generates a pattern match output if all of the sub-word FSMs indicate a match to the pattern. The pattern is a variable pattern. In one embodiment, the FSMs are single bit FSMs.

Abstract: A measurement instrument receives an analog input signal from a measurement target, converts the input signal into a digital signal, scans the digital signal and comparing the scanned digital signal with a pattern signature using a flexible matching procedure implemented by hardware, and triggers the measurement instrument according to a result of the flexible matching procedure.

Abstract: A network element is provided with the capability to perform monitoring and/or measurement functions on the element and the network of which it is a part. The monitoring/measurement functionality is implemented by programmable devices to enable the functionality to be modified and updated without removing the network element from service.