Abstract: A data stream search system can include a plurality of search data inputs logically divided into at least M+N sets. The sets have a logical order with respect to one another, each set providing more than one bit value. A key application circuit can comprise a plurality of data paths that each couple a different group of at least M data input sets to a corresponding content addressable memory (CAM) section. Each different group of at least M data input sets can be contiguous with respect to the logical order, and shifted in bit order from one another by at least two bits.

Abstract: A processing system includes a network processor and a CAM device having a re-entrant processor coupled to a CAM array. The re-entrant processor is configured to selectively modify an initial search key provided by the network processor by replacing portions of the initial search key with portions of one or more previous search keys and/or one or more previous results. The re-entrant processor is also configured to initiate a series of subsequent compare operations between new search keys and data stored in the CAM array without receiving additional instructions or search keys from the network processor.

Abstract: A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.

Abstract: A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed.

Abstract: Disclosed is a texture prefetching method for use in a three-dimensional graphics display system in which texture maps of an object are stored in memory for texels at (u,v) memory locations. The method of fetching texels for use in calculating (x,y) display pixel values comprises the steps of: a) identifying in (u,v) space a geometric shape to be displayed in (x,y) space, b) establishing tiles of pixels within the geometric shape for use in accessing texels, c) computing texel addresses at one side of a tile based on current addresses (topuc, topvc) and first and second derivatives of (u,v) as a function of (x) and a first derivative as a function of (y), d) computing texel addresses at an opposing side of the tile based on current addresses (u0,v0) and first and second derivatives of (u,v) as a function of (x) and a first derivative as a function of (y), and e) fetching texel blocks within the tiles as defined by the addresses in steps c) and d).

Abstract: A reciprocal generator is useful for perspective correction for 3D graphics. The input range is divided into many sections. A lookup table contains reciprocal outputs for only two of the sections, the smallest-inputs section and the largest-inputs section. Entries in the table for the smallest section contain a base and a scale factor to indicate the reciprocal value. One entry is provided for each possible input value in the smallest section. This provides high precision where the outputs have the largest values, reducing visible distortions caused by relatively small changes in the large output values. Each section is divided into intervals, with one table entry for each interval. For the largest section, each table entry has an initial reciprocal and a slope of a line approximating the reciprocal curve in that interval. Reciprocals for inputs within the interval are calculated by multiplying an offset into the interval by the slope, and then adding to the initial reciprocal for that interval.

Abstract: A 3D graphics processor has parallel triangle pixel pipelines. One or more triangle setup engine(s) receives triangle primitives from a host or geometry engine and generates vertex color, texture and other attributes as well as their gradients. The triangle setup engine makes available all required triangle data to the triangle pixel pipelines. The triangle pixel pipelines accept the next triangle data on a demand basis, when finished with the previous triangle. Each triangle pixel pipeline has a span engine that generates endpoints along the 3 edges of the triangle where the horizontal lines (spans) intersect. Each triangle pixel pipeline also has a raster engine that receives the endpoints as well as gradients and generates color, texture and other attributes for each pixel along a span between endpoints. The raster engine then composites pixels from these attributes and updates visible pixels in the frame buffer.

Abstract: A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed.

Abstract: A system using a ray-tracing algorithm and a hierarchy of volume elements (called voxels) to process only the visible surfaces in a field of view. In this arrangement, a dense, three-dimensional voxel data base is developed from the objects, their shadows and other features recorded, for example, in two-dimensional aerial photography. The rays are grouped into subimages and the subimages are executed as parallel tasks on a multiple instruction stream and multiple data stream computer (MIMD). The use of a three-dimensional voxel data base formed by combining three-dimensional digital terrain elevation data with two-dimensional plan view and oblique view aerial photography permits the development of a realistic and cost-effective data base. Hidden surfaces are not processed. By processing only visible surfaces, displays can now be produced depicting the nap-of-the-earth as seen in low flight of aircraft or as viewed from ground vehicles.

Abstract: A computer which achieves highly parallel execution of programs in instruction flow form, as distinguished from data flow form employing a unique computer architecture in which the individual units such as, process control units, programmable function units, memory units, etc., are individually coupled together by an interconnection network as self-contained units, logically equidistant from one another in the network, to be shared by any and all resources of the computer. All communications among the units now take place on the network. The result is a highly parallel and pipelined computer capable of executing instructions or operations at or approaching full clock rates.Each process control unit initiates its assigned processes in sequence, routing the first instruction packet of each process through the network and addressed memories and function units back to the initiating process control unit where it is relinked with its process.

Abstract: A packet switching node which processes applied data packets containing routing tag signals indicative of the output port destination to which the data packets are to be applied. The invention comprises an N.times.M switch node that accepts data packets at any of N input ports and routes each to any of M output ports. The output selected is determined by the routing tag signal in the packet. The node comprises a multiport memory having a predetermined number of memory locations available for storage of data packets applied to each of a plurality of input ports. Control logic coupled to the input and output ports and memory is designed so that the data packets are effectively sorted according to their desired output port destination. The control logic comprises arbitration logic which randomly, in a statistical sense, chooses among any data packets that are directed to the same output port.