Abstract: Systems, methods, and compositions of blended beverages are provided herein. Exemplary compositions are a blended beverage including a cannabidiol (CBD) crystalline isolate suspended in an alcoholic beverage, the alcoholic CBD beverage being a concentration of least 20 milligrams of CBD crystalline isolate per cubic centimeter of the beverage. In various embodiments the alcoholic CBD beverage is a wine, a spirit, or a beer.

Abstract: Medical devices and methods are disclosed in the present application. In one illustrative example a cell sample collection device may comprise an elongated shaft extending from a proximal end to a distal end and a tissue collection feature extending distal of the distal end of the elongated shaft. In at least some additional embodiments, at least a portion of the tissue collection feature may dissolve when placed in a fixation medium.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: An improved clock generator performs clock multiplication using selectable generation of clock edges. A clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock—these edges are selectably combined to produce an output clock with the desired multiplication and duty cycle. The sequence of non-overlapping pulses is synchronized to the period of the input reference clock, i.e., to the first harmonic of the reference clock. A pulse generator network includes N pulse generators PG1-PGN, with the output of each pulse generator being coupled to the input of the next pulse generator. When triggered, each pulse generator generates a pulse P with a leading edge and a trailing edge, and a pulse width determined by a selectable pulse-width delay signal.

Abstract: A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a hardware interface that interfaces directly to the processor local-bus--a Qbuffer protocol using conventional byte enable signals provides lane steering to eliminate the need for separate multiplexing logic. The Qbuffer protocol signals include a BE control signal asserted by the system logic to cause the CPU to relinquish control of the byte enable control lines, such that the system control logic is able to drive the BE control lines with byte enable codes to implement lane steering for CPU-Peripheral transfers.

Abstract: A precision Z-interpolator for use in an interactive graphics system multiplies the line slope by a value f.sub.S in computing the first Z ordinate value. This eliminates the offset error in Z inherent in previously known interpolators. For extremely large slopes, the slope is not used directly in the computations. Instead the value used is (Z.sub.E -Z.sub.S)/(1+f.sub.E /f.sub.S) (see FIG. 4).