Abstract: A data communications device interconnected for channelized communication overcomes the problems associated with message traffic starvation on outgoing traffic channels by forming arbitration, or speed groups of logical interfaces and allocating scheduling resources in proportion to the bandwidth attributed to each group relative to the total bandwidth of the device. Incoming messages have a transmission rate based on QOS, content type, or other constraints. A categorizer determines arbitration groups of the outgoing messages based on the transmission rate of the message. The scheduler allocates dequeue requests among the groups according to the proportion allocated to the arbitration group. A dequeue manager drains the outgoing messages from the arbitration groups at a rate in proportion to the total percentage of outgoing transmission bandwidth represented by the group by selecting a message from among the arbitration groups according to the computed proportion.

Abstract: Typically, queues in a router device are used to track data information such as packets or data flows for later transmission to another downstream communication device. To reduce overhead associated with tracking an average queue length of a queue, a metric reflecting average queue length (or estimated queue length) is updated based on the occurrence of an event such as when the contents of the queue are modified. More specifically, if data is added or deleted from the queue, the metric reflecting an average fullness of the queue over time is updated at substantially the same time as updating the instantaneous queue length metric associated with the queue. This technique of synchronously updating both IQL and AQL simplifies the overall task of maintaining queue length information.

Abstract: Conventional schedulers employ designs allocating specific processor and memory resources, such as memory for configuration data, state data, and scheduling engine processor resources for specific aspects of the scheduler, such as layers of the scheduling hierarchy, each of which consumes dedicated processor and memory resources. A generic, iterative scheduling engine, applicable to an arbitrary scheduling hierarchy structure having a variable number of hierarchy layers, receives a scheduling hierarchy structure having a predetermined number of layers, and allocates scheduling resources such as instructions and memory, according to scheduling logic, in response to design constraints and processing considerations.

Abstract: A Route Lookup Engine (RLE) for determining a next hop index is disclosed. The RLE receives a lookup key and performs a multi-bit trie search with prefix expansion and capture of a variable stride trie. The data that the RLE returns comprises the next hop information and status flags. The RLE uses a compact, field reusable data structure. The RLE performs both unicast and multicast IP address lookups on Virtual Private Networks. The RLE uses separate indexing and forwarding memories. The upper bound of the search time for the RLE is fixed regardless of the route table size.

Abstract: A method is presented which allows for the testing and verification of an off-line switch fabric used in network switch having redundant switch fabrics. A special test cell is directed to the off-line switch fabric, loops through a portion of the switching core of the off-line switch fabric, and is returned from the off-line switch fabric. A plurality of test cells can be used to provide full mesh connectivity checking of the off-line switch fabric. Testing is accomplished without need for reconfiguration of the off-line switch fabric, and the off-line switch fabric is available for use immediately upon determination of the need therefor.

Abstract: Packet classification apparatus includes a rule memory and a criterion memory. One type of rule memory entry contains an operator and a pointer to a criterion memory entry. The operator defines a comparison operation to be performed, such as EQUAL (exact match) or LESS THAN. The criterion memory entry contains one or more values to be used as comparands on one side of the comparison, where corresponding values from a received packet appear on the other side of the comparison. Control logic responds to packet classification requests to retrieve a rule memory entry from the rule memory, retrieve the criterion memory entry identified by the criterion memory pointer in the rule memory entry, and perform the operation specified by the operator in the rule memory entry on the values in the criterion memory entry and corresponding values included in the classification request.

Abstract: Packet processing logic includes a request queue for receiving lookup requests from a packet processor, where each request includes information elements from a received packet and indicates that a route lookup and a packet classification are to be performed based on the information elements. Both a route lookup engine (RLE) and a packet classification engine (PCE) have respective inputs coupled to the request queue for receiving selected information elements from the requests. Based on the information elements in each request, the RLE searches for forwarding information indicating how the packet corresponding to the request should be forwarded, and the PCE performs a classification process and generates classification information about the packet corresponding to the request. For each request, the forwarding information from the RLE and the classification information from the PCE are combined into a single result stored in a result queue.

Abstract: A method and apparatus for performing logical multicasting within a network switch are disclosed so as to permit a downstream network device to perform cell forwarding in a manner which resembles spatial multicasting. A logical multicast cell has a connection identifier associated with the cell within the switch. The connection identifier is employed to initiate a series of lookup operations to generate unique VPI/VCI addresses which are transmitted out of an output port of the switch as copies or leaves of the multicast cell. Successive look-ups of outgoing VPI/VCI addresses for a logical multicast cell are performed using a chain bit to indicate when all leaves of the cell have been transmitted. Leaves of a logical multicast cell are transmitted to the downstream network device from one output cell buffer of a plurality of output cell buffers associated with the output port of the switch so as to minimize the likelihood of blocking and so as to minimize cell delay variation.

Abstract: Improved methods and apparatus are disclosed for remapping Asynchronous Transfer Mode ("ATM") cells in an ATM switch to convert a single Virtual Path Identifier ("VPI")/Virtual Connection Identifier ("VCI") address pair to multiple outgoing VPI/VCI pairs for multicast transmission. An incoming cell is examined to determine the ports through which the cell will exit and a local header is generated which includes a field specifying the I/O modules ("IOMs") through which the cell will exit. The VPI/VCI pair of an incoming multicast cell is mapped to a global multicast identifier ("MID") which is written into the local header. The cell, including the local header is then forwarded to the IOMs specified in the header. A first lookup table on each IOM is employed to provide a port bitmask indexed by MID to direct the cell to the previously identified ports, and to map the MID into a connection identifier ("CID").

Abstract: A method and apparatus for performing address translation in an ATM network element, such as a switch, resulting in minimized circuit complexity and resultant cost savings. The present invention includes the generation of a simplified local address from elements of internetwork communications, the local address being suitable for addressing a routing table in the network element. Components of the local address are also individually employed as masks for out-of-range checking.