Abstract: A dynamic error introduced by track-and-hold circuits can be reduced by using an input signal derivative to perform linear extrapolation during the hold period, allowing the output of the track-and-hold circuit to provide improved performance in reconstructing an undistorted input waveform, or to perform other applications such as demultiplexing. As described herein, a track-and-hold circuit and related techniques can include use of a first-order (e.g., linear) extrapolation. A first-order extrapolation can better approximate or reconstruct a signal during a specified hold duration, as compared to a zeroth-order technique. Use of analog circuits to implement the first-order extrapolation can one or more of reduce complexity of a circuit implementation or improve performance, such as by not requiring digital signal processing circuitry in performing the extrapolation.

Abstract: A dynamic error introduced by track-and-hold circuits can be reduced by using an input signal derivative to perform linear extrapolation during the hold period, allowing the output of the track-and-hold circuit to provide improved performance in reconstructing an undistorted input waveform, or to perform other applications such as demultiplexing. As described herein, a track-and-hold circuit and related techniques can include use of a first-order (e.g., linear) extrapolation. A first-order extrapolation can better approximate or reconstruct a signal during a specified hold duration, as compared to a zeroth-order technique. Use of analog circuits to implement the first-order extrapolation can one or more of reduce complexity of a circuit implementation or improve performance, such as by not requiring digital signal processing circuitry in performing the extrapolation.

Abstract: A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from the values of the data bits in accordance with a predefined algorithm which enables the detection of at least one data bit error, receiving the data bits and error correction bits, deriving a second set of error correction bits from the values of the received bits in accordance with the predefined algorithm, comparing the first and second sets of error correction bits to detect the presence of data bit errors in the received data bits, correcting the data bit errors in the received data bits, and providing the corrected received data bits to the at least one analog circuit.

Abstract: A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from the values of the data bits in accordance with a predefined algorithm which enables the detection of at least one data bit error, receiving the data bits and error correction bits, deriving a second set of error correction bits from the values of the received bits in accordance with the predefined algorithm, comparing the first and second sets of error correction bits to detect the presence of data bit errors in the received data bits, correcting the data bit errors in the received data bits, and providing the corrected received data bits to the at least one analog circuit.

Abstract: A single-wire digital interface for receiving digital data as a stream of pulses, with ‘1’ and ‘0’ logic levels represented with pulses having “first” and “second” pulse widths, respectively. A low-pass filter produces an output that increases at a known rate for the duration of a received data pulse, and a comparator produces an output that toggles when the filter output exceeds a predetermined threshold. A clock edge is generated when a received pulse terminates; the clock and comparator outputs are provided to a latch circuit. The interface latches a ‘1’ when the received pulse's width is equal to the “first” pulse width, and latches a ‘0’ when the received pulse's width is equal to the “second” pulse width. Data is preferably preceded by a “start-of-packet” (SOP) bit pattern and followed with a “end-of-packet” (EOP) bit pattern.

Abstract: A programmable fuse state determination system and method provide a fuse current through a programmed fuse which produces a voltage that varies with the fuse's resistance. The voltage is compared with a threshold voltage to indicate whether the fuse is blown or intact. The invention employs ‘normal’ and ‘test’ modes, in which the relationship between the fuse's resistance and the threshold voltage differ, such that a higher fuse resistance is required for the fuse to be determined blown in the ‘test’ mode than in the ‘normal’ mode.

Abstract: A current integration circuit includes an operational amplifier having a capacitor connected between its output and inverting input which integrates an input current. To prevent the op amp's output from becoming saturated, a charge dumping circuit dumps a known charge of the opposite polarity to that stored on the capacitor to the op amp's inverting input, thus reducing the charge on the capacitor and preventing the op amp's output from becoming saturated. A charge dump is triggered whenever the op amp's output exceeds a predetermined trip voltage. Counting the number of charge dumps performed during a given integration period provides a coarse indication of the magnitude of the integrated input current, and the output of the op amp provides a fine indication.

Abstract: An auto-ranging current integration circuit includes an operational amplifier which receives an input current to be integrated, and an array of integration capacitors which are switchably connected in parallel between the op amp's output and inverting input. A control circuit initially connects a first capacitor across the op amp, and then connects additional capacitors in parallel with the first whenever the op amp's output exceeds a predetermined voltage, but before the output becomes saturated. In this way, a smaller integration capacitance is automatically employed for a small input current, and larger capacitance values are automatically switched in for larger input currents, which lowers the integration gain, prevents the output from saturating, and keeps the current integration circuit's signal-to-noise ratio high.

Abstract: A ping-pong amplifier includes two differential amplifiers A1 and A2 and an error amplifier. The error amplifier has one input connected to a predetermined common-mode reference voltage VCMR, its other input switchably connected to the common-mode outputs of A1 or A2, and an output which is switchably connected to the common-mode reference (CMR) voltage inputs of A1 and A2. Respective memory capacitors CM1 and CM2 are connected to the two CMR inputs. The error amplifier is periodically connected between A1's common-mode output and its CMR input to form a closed-loop which forces A1's common-mode output voltage to be equal to VCMR, with the error amplifier's output voltage stored on CM1. A2's common-mode output voltage is similarly calibrated, with the error amplifier's output voltage stored on CM2. Both common-mode output voltages are thus made equal to VCMR, thereby reducing transients that might otherwise appear in the output as the amplifier ping-pongs between A1 and A2.

Abstract: A ping-pong amplifier employs auto-zeroing and chopping to simultaneously achieve low offset voltage and low frequency noise, as well as low energy at the chopping frequency. The ping-pong amplifier includes respective nulling amplifiers for each of its gain amplifiers, which auto-zero each gain amplifier. In addition, switches are included which allow the inputs and outputs of the active gain amplifier to be chopped. Thus, while one gain amplifier is being auto-zeroed, the other gain amplifier amplifies the input signal and its inputs and outputs are chopped. One of the described embodiments includes circuitry which reduces switching transients that might otherwise appear in the amplifier's output by ensuring that the common-mode output voltage of each gain amplifier is kept equal to a common-mode reference voltage.

Abstract: The chopping frequency driving a chopper-stabilized amplifier (CSA) is dynamically varied between an upper and lower frequency limit to reduce the intermodulation distortion, clock noise and low-frequency noise found in prior art designs. The upper limit is set to accommodate the settling times required by the CSA's memory capacitors, and the lower limit is set to a non-zero frequency significantly greater than DC to reduce low frequency noise. The two limits permit IMD and clock noise to be widely scattered and enable a near optimum trade off between IMD and chopping noise on one hand, and low frequency noise on the other. The chopping frequency is preferably generated digitally with a loadable counter which divides down a fixed frequency master clock, with the binary value presented at the counter's load inputs periodically varied to dynamically vary the division ratio and thus frequency modulate the chopping frequency.