Abstract: A system for supporting castings during thermal treatments, such as solution heat treatment, quenching and aging, that includes a tray defining a horizontal base plane and having a plurality of tray openings therethrough, and a fixture extending over one or more of the tray openings. The fixture is formed by a plurality of support plates oriented vertically with lower portions extending across the tray opening and top edges extending above the tray opening with shaped profiles along the lengths thereof. The plurality of support plates form an open lattice having a plurality of top edges that together define an open support surface that is substantially complementary with an underside surface of a casting and configured to loosely support the casting atop the lattice and align the casting in space above the tray opening.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Abstract: The invention relates to a collapsible luggage bag that improves maneuverability of the bag when a user is towing the bag and collapses to a reduced size to improve portability. In particular, the invention relates to a handle that is slideably interconnected to one or more stays such that the upper ends of the stays change position along the length of the handle as the handle retracts into the luggage. Further, the handle disconnects from one or more of the stays such that the handle, stays, and other frame components collapse and lie in a common plane. This collapsibility improves the portability of the luggage bag when the internal volume of the luggage bag is not used to store items.

Abstract: An antenna with a clamping mechanism and a method for using the same are disclosed. In one embodiment, an antenna comprises a radial waveguide, an aperture operable to radiate radio frequency (RF) signals in response to an RF feed wave fed by the radial waveguide, and one or more clamping devices to apply a compressive force between the waveguide and the aperture.

Abstract: According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Abstract: A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.

Abstract: Disclosed herein is a method for failure signature detection in a semiconductor comprising generating defect signatures for failing latches from a plurality of integrated circuit chips; generating a latch to mask relationship for the failing latches; generating maximally descriptive masks into identities; generating a list of identities for comparison; determining commonalities between the lists of identities; and generating details about differences and commonalities within the defect signatures.

Abstract: Disclosed are certain derivatives of benzoxazinone amides of formula (I), or pharmaceutically acceptable salts thereof, (Formula (I)) that act as mineralocorticoid (MR) receptor modulators that may reduce oxidative stress in endothelium and hence improve vascular function, to methods for their potential therapeutic use, to pharmaceutical compositions containing them and to processes for preparing such compounds.

Abstract: In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

Abstract: A method and apparatus is disclosed herein for supporting an antenna and its components. In one embodiment, a retention apparatus for use in coupling to an antenna aperture during manufacturing comprises: a base plate; a plurality of clamps coupled to the base plate, each clamp of the plurality of clamps being rotatable to couple the antenna aperture to the base plate; and one or more component holders coupled to the base plate, each of the one or more component holders to securely hold at least one component that is coupled to the antenna aperture.

Abstract: In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

Abstract: Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.