Patents by Inventor Andrew Vogan
Andrew Vogan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8954650Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.Type: GrantFiled: September 16, 2011Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Hanmant P. Belgal, Ning Wu, Paul D. Ruby, Andrew Vogan, Xin Guo, Ivan Kalastirsky, Mase J. Taub
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Patent number: 8631187Abstract: A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space.Type: GrantFiled: August 7, 2009Date of Patent: January 14, 2014Assignee: Intel CorporationInventor: Andrew Vogan
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Publication number: 20130073786Abstract: Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Inventors: Hanmant P. Belgal, Ning Wu, Paul D. Ruby, Andrew Vogan, Xin Guo, Ivan Kalastirsky, Mase J. Taub
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Publication number: 20120166686Abstract: A memory controller, and/or operation thereof, to generate a single interrupt for a plurality of data blocks which are the subject of a data transfer request. In an embodiment, a set of flags is allocated for the data transfer request, each flag corresponding to a respective one of the plurality of data blocks. In another embodiment, a single hardware interrupt is generated for all data which is the subject of the data transfer request, the generating based on an evaluation of the allocated set of flags.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: Joerg Hartung, Andrew Vogan
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Patent number: 8001444Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.Type: GrantFiled: August 8, 2007Date of Patent: August 16, 2011Assignee: Intel CorporationInventors: Andrew Vogan, Jawad B. Khan, Sowmiya Jayachandran
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Patent number: 7966456Abstract: Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk.Type: GrantFiled: September 28, 2007Date of Patent: June 21, 2011Assignee: Intel CorporationInventors: Sanjeev N. Trika, Rick Mangold, Andrew Vogan
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Publication number: 20110035534Abstract: A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space.Type: ApplicationFiled: August 7, 2009Publication date: February 10, 2011Inventor: Andrew Vogan
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Patent number: 7694071Abstract: A disk drive capable of being configured into a plurality of data storage zones, wherein some of the zones have different performance characteristics than other zones; a method for performing such a zoning configuration; and, a host device utilizing such a disk drive. The disk drive comprises a disk having a plurality of sectors for storing data, a head for reading and writing the data, and a disk drive controller for controlling the head, wherein the plurality of the sectors are organized into the plurality of zones. In one embodiment of the present invention, the performance characteristics of the zones are dictated by configuration settings in the disk drive controller. The configuration settings may include settings for a plurality of parameters. In some embodiments of the present invention, the plurality of parameters comprises a CCT (command completion time) parameter, a Write Verify parameter, a Write Continuous parameter, a Read Continuous parameter, and an Error Re-allocation parameter.Type: GrantFiled: July 11, 2006Date of Patent: April 6, 2010Assignee: Seagate Technology LLCInventors: Jasbir Sidhu, Andrew Vogan
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Publication number: 20090089508Abstract: Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: INTEL CORPORATIONInventors: Sanjeev N. Trika, Rick Mangold, Andrew Vogan
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Publication number: 20090044078Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Inventors: Andrew Vogan, Jawad B. Khan, Sowmiya Jayachandran
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Patent number: 7345837Abstract: A disk drive includes a rotatable data storage disk, a transducer, an actuator, and a controller. The transducer is configured to read and write data on the disk. The actuator is configured to position the transducer relative to defined portions of the disk. The controller is configured to determine how many times data has been written to the defined portions of the disk. The controller is also configured to refresh data residing at a particular one of the defined portions of the disk when the number of times data has been written to the particular defined portion of the disk satisfies a threshold value.Type: GrantFiled: July 19, 2005Date of Patent: March 18, 2008Assignee: Maxtor CorporationInventors: Erhard Schreck, Donald Brunnett, Hung V. Nguyen, Bruce Schardt, Andrew Vogan
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Publication number: 20070143536Abstract: A data storage device includes a data storage media, a head, a data fetch buffer, and a controller. The head is configured to read data stored in logical block addresses (LBA) on the media. The data fetch buffer is configured to store data. The controller is configured to read data through the head from LBAs on the media that are identified by LBA access sequence information in the data storage device which identifies a sequence of LBAs that a host device will access and to store the read data in the data fetch buffer. The controller is also configured to respond to a read command from the host device that is directed to data at a LBA of the media that is identified the LBA access sequence information and which has been read into the data fetch buffer by communicating the data associated with the read command from the data fetch buffer to the host device.Type: ApplicationFiled: February 13, 2006Publication date: June 21, 2007Inventors: Jasbir Sidhu, Andrew Vogan
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Patent number: 7065613Abstract: The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area of the cache. In another embodiment, the invention prevents reading previous line data for a new tag from main memory when the new tag represents a currently unused area of the cache.Type: GrantFiled: June 6, 2003Date of Patent: June 20, 2006Assignee: Maxtor CorporationInventors: Lance Flake, Andrew Vogan