Patents by Inventor Andrew W. Metz
Andrew W. Metz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11121027Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.Type: GrantFiled: December 7, 2018Date of Patent: September 14, 2021Assignee: Tokyo Electron LimitedInventors: Yen-Tien Lu, Xinghua Sun, Eric Chih-Fang Liu, Andrew W. Metz
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Patent number: 10854453Abstract: A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.Type: GrantFiled: June 11, 2018Date of Patent: December 1, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Angelique D. Raley, Christopher Cole, Andrew W. Metz
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Patent number: 10438797Abstract: Techniques herein include an etch process that etches a layer of material incrementally, similar to mono-layer etching of atomic layer etching (ALE), but not necessarily including self-limiting, mono-layer action of ALE. Such techniques can be considered as quasi-atomic layer etching (Q-ALE). Techniques herein are beneficial to precision etching applications such as during soft-mask open. Techniques herein enable precise transfer of a given mask pattern into an underlying layer. By carefully controlling the polymer deposition relative to polymer assisted etching through its temporal cycle, a very thin layer of conformal polymer can be activated and used to precisely etch and transfer the desired patterns.Type: GrantFiled: September 6, 2017Date of Patent: October 8, 2019Assignee: Tokyo Electron LimitedInventors: Hongyun Cottle, Andrew W. Metz
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Patent number: 10332744Abstract: Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.Type: GrantFiled: April 28, 2017Date of Patent: June 25, 2019Assignee: Tokyo Electron LimitedInventors: Anton J. deVilliers, Andrew W. Metz
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Publication number: 20190181041Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.Type: ApplicationFiled: December 7, 2018Publication date: June 13, 2019Inventors: Yen-Tien Lu, Xinghua Sun, Eric Chih-Fang Liu, Andrew W. Metz
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Publication number: 20180358227Abstract: A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.Type: ApplicationFiled: June 11, 2018Publication date: December 13, 2018Inventors: Angelique D. Raley, Christopher Cole, Andrew W. Metz
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Publication number: 20180068852Abstract: Techniques herein include an etch process that etches a layer of material incrementally, similar to mono-layer etching of atomic layer etching (ALE), but not necessarily including self-limiting, mono-layer action of ALE. Such techniques can be considered as quasi-atomic layer etching (Q-ALE). Techniques herein are beneficial to precision etching applications such as during soft-mask open. Techniques herein enable precise transfer of a given mask pattern into an underlying layer. By carefully controlling the polymer deposition relative to polymer assisted etching through its temporal cycle, a very thin layer of conformal polymer can be activated and used to precisely etch and transfer the desired patterns.Type: ApplicationFiled: September 6, 2017Publication date: March 8, 2018Inventors: Hongyun Cottle, Andrew W. Metz
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Patent number: 9818610Abstract: A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.Type: GrantFiled: March 14, 2017Date of Patent: November 14, 2017Assignee: Tokyo Electron LimitedInventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
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Publication number: 20170316939Abstract: Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.Type: ApplicationFiled: April 28, 2017Publication date: November 2, 2017Inventors: Anton J. deVilliers, Andrew W. Metz
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Publication number: 20170263443Abstract: A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.Type: ApplicationFiled: March 14, 2017Publication date: September 14, 2017Inventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
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Patent number: 9607834Abstract: A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer.Type: GrantFiled: April 1, 2016Date of Patent: March 28, 2017Assignee: Tokyo Electron LimitedInventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
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Publication number: 20160293405Abstract: A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer.Type: ApplicationFiled: April 1, 2016Publication date: October 6, 2016Inventors: Hiroie Matsumoto, Andrew W. Metz, Yannick Feurprier, Katie Lutker-Lee
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Patent number: 9396958Abstract: Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield.Type: GrantFiled: September 25, 2015Date of Patent: July 19, 2016Assignee: Tokyo Electron LimitedInventors: Andrew W. Metz, Anton J. deVilliers
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Publication number: 20160104628Abstract: Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield.Type: ApplicationFiled: September 25, 2015Publication date: April 14, 2016Inventors: Andrew W. Metz, Anton J. deVilliers
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Patent number: 8808562Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.Type: GrantFiled: September 12, 2011Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventors: Yusuke Ohsawa, Hiroto Ohtake, Eiji Suzuki, Kaushik Arun Kumar, Andrew W. Metz
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Patent number: 8501630Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.Type: GrantFiled: September 28, 2010Date of Patent: August 6, 2013Assignee: Tokyo Electron LimitedInventors: Andrew W. Metz, Hongyun Cottle
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Publication number: 20130065398Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.Type: ApplicationFiled: September 12, 2011Publication date: March 14, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Yusuke OHSAWA, Hiroto OHTAKE, Eiji SUZUKI, Kaushik Arun KUMAR, Andrew W. METZ
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Patent number: 8382997Abstract: A method of patterning a substrate is described. The method includes preparing a film stack on a substrate, wherein the film stack comprises a spin-on layer, and heating the spin-on layer to a cure temperature less than a thermal decomposition temperature of the spin-on layer and exceeding about 200 degrees C. to increase mechanical strength of the spin-on layer. The method further includes forming a feature pattern without pattern collapse in the spin-on layer, wherein the feature pattern is characterized by a critical dimension less than 35 nm (nanometers) and an aspect ratio relating a height of the feature pattern to the critical dimension exceeding 5:1.Type: GrantFiled: August 16, 2010Date of Patent: February 26, 2013Assignee: Tokyo Electron LimitedInventor: Andrew W. Metz
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Publication number: 20120077347Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Andrew W. METZ, Hongyun COTTLE
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Publication number: 20120037592Abstract: A method of patterning a substrate is described. The method includes preparing a film stack on a substrate, wherein the film stack comprises a spin-on layer, and heating the spin-on layer to a cure temperature less than a thermal decomposition temperature of the spin-on layer and exceeding about 200 degrees C. to increase mechanical strength of the spin-on layer. The method further includes forming a feature pattern without pattern collapse in the spin-on layer, wherein the feature pattern is characterized by a critical dimension less than 35 nm (nanometers) and an aspect ratio relating a height of the feature pattern to the critical dimension exceeding 5:1.Type: ApplicationFiled: August 16, 2010Publication date: February 16, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Andrew W. METZ