Abstract: A system and method for processing a video signal to make the corresponding image suitable for display on a progressive display device, i.e., a computer monitor, is disclosed. The processing system includes a video display module which is capable of processing an image frame based on the content of the frame information itself, or the values of the pixels that comprise the frame.

Abstract: A method for determining the integrity of an application program running on a computer system includes the preallocation of memory segments in the data portion for holding tables. Relocation addresses are selected and extracted from relocatable object programs, libraries and modules during translation and inserted into the tables. Additionally, a default address of a subprogram is selected and stored in the data portion. During execution of the application program, a run time reference address of the subprogram is determined and compared with the stored default address. If a match occurs, the reference address is used when performing a checksum of the application program. This occurs even for the situation of non-relocatable code. Otherwise, the reference address and the default address are used to offset the memory contents of relocation addresses stored in the tables for the purposes of performing a security application on the program.

Abstract: A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio, FAX/modem, telephony, and video-conferencing. In accordance with the present invention, a media engine includes a signal processor which shares a memory with the CPU of the host computer and also includes a plurality of control modules each dedicated to one of the seven multi-media functions. The signal processor retrieves from this shared memory instructions placed therein by the host CPU and in response thereto causes the execution of such instructions via one of the on-chip control modules. The signal processor utilizes an instruction register having a movable partition which allows larger than typical instructions to be paired with smaller than typical instructions.