Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract: Automatic antenna diode insertion for integrated circuits is described. In an example, at least a portion of an integrated circuit is defined by a block of standard cells selected from a cell library. A diode circuit is associated with at least one input port of the block of standard cells to form an augmented block. The augmented block is then implemented on a chip to form the integrated circuit. In another example, an integrated circuit is formed by associating a diode circuit with each primary input port of an embedded logic circuit that defines a portion of the integrated circuit. A remaining portion of the integrated circuit is defined by existing logic circuitry. Components of the embedded logic circuit are placed on a chip and conductors are routed connecting the components. The embedded logic circuit is then integrated with the existing circuitry onto the chip.

Abstract: Generation of consistent connection data for a first circuit embedded in a second circuit. In one approach, a master file is established with design data that includes for each pin in the embedded circuit, a hardware description language (HDL) pin name from an HDL description of the embedded circuit, a schematic pin name of the second circuit to which a corresponding pin in the embedded circuit is to connect, a signal direction associated with the pin, and a name of a clock to trigger a signal on the pin. A plurality of design views are generated from the master file. Each design view has a unique format relative to the other design views and includes for each pin in the embedded circuit design, at least the HDL pin name, the associated schematic pin name, and a signal direction associated with the pin.

Abstract: Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket module for coupling an embedded device to a host device, and each of these sub-process may be limited to a lithographic process dimension or adjusted accordingly. By dividing timing information gathering into sub-process, output from each of the sub-process may be combined with timing information provided with an embedded core to determine path delays.

Abstract: Method and apparatus for placement of vias is described. More particularly, source power and ground vias are placed in partial response to locations where conductive lines cross over a reserved region. The reserved region is reserved for an embedded device, and is reserved in a layout database of a host device.

Abstract: Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations.

Abstract: Method for configuring a routing program for routing connections between an integrated circuit device and an embedded core is described. More particularly, horizontal and a vertical pitch are obtained for the integrated circuit device and the embedded core. A horizontal or a vertical pitch is selected from the embedded core to define pitch for the integrated circuit device to accommodate difference in pitch between the two. Additionally, an integrated circuit having interconnect layers using this compromise pitch are described.

Abstract: Method and apparatus for an insertable block tile is described. More particularly, a reserved area in an integrated circuit layout is removed, and terminated conductive line information is extracted from a layout database affected by the removal. The terminated conductive line information is used to create extensions or pins of the conductive lines terminated, as well as to identify signals associated with those terminated conductive lines. These physical or layout names and coordinates are mapped and then translated to logic names and coordinates for placement and routing to create the insertable block tile.

Abstract: Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations.

Abstract: Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations.

Abstract: Described is a method of using place-holding cells, or “stopper cells,” to force a place-and-route tool to route a selected signal path through a particular physical location on a semiconductor die. In one method, phantom blocks, created from the design specification, define the area, logic, timing, and the placement of input/output (I/O) ports for a number of custom blocks. These phantom blocks are combined with any standard blocks to create a high-level description of a desired circuit. Then, for each I/O port of the custom blocks, a place-holding cell, or “stopper cell,” is added to the description in the path defined between the I/O port and its source or destination. The stopper cells are then grouped with the associated custom blocks and the resulting collection of stopper cells and blocks are placed and routed. Completed custom blocks can then be substituted for respective phantom blocks after place and route. Stopper cells preserve complex routing during this substitution.