Abstract: The present disclosure relates to a neural network system comprising: a controller including a processing unit configured to execute a spiking neural network, and an interface connecting the controller to an external memory. The controller is configured for executing the spiking neural network, the executing comprising generating read instructions and/or write instructions. The interface is configured for: generating read weighting vectors according to the read instructions, coupling read signals, representing the read weighting vectors, into input lines of the memory, thereby retrieving data from the memory, generating write weighting vectors according to the write instructions, coupling write signals, representing the write weighting vectors, into output lines of the memory, thereby writing data into the memory.

Abstract: The present disclosure relates to a neuromorphic neuron apparatus comprising an output generation block and at least one adaptation block. The apparatus has a current adaptation state variable corresponding to previously generated one or more signals. The output generation block is configured to use an activation function for generating a current output value based on the current adaptation state variable. The adaptation block is configured to repeatedly: compute an adaptation value of its current adaptation state variable using the current output value and a correction function; use the adaption value to update the current adaptation state variable to obtain an updated adaptation state variable, the updated adaptation state variable becoming the current adaptation state variable; receive a current signal; and cause the output generation block to generate a current output value based on the current adaptation state variable and input value that obtained from the received signal.

Abstract: Neuromorphic methods, systems and devices are provided. The embodiment may include a neuromorphic device which may comprise a crossbar array structure and an analog circuit. The crossbar array structure may include N input lines and M output lines interconnected at junctions via N×M electronic devices, which, in preferred embodiments, include, each, a memristive device. The input lines may comprise N1 first input lines and N2 second input lines. The first input lines may be connected to the M output lines via N1×M first devices of said electronic devices. Similarly, the second input lines may be connected to the M output lines via N2×M second devices of said electronic devices. The analog circuit may be configured to program the electronic devices so as for the first devices to store synaptic weights and the second devices to store neuronal states.

Abstract: In a hardware-implemented approach for operating a neural network system, a neural network system is provided comprising a controller, a memory, and an interface connecting the controller to the memory, where the controller comprises a processing unit configured to execute a neural network and the memory comprises a neuromorphic memory device with a crossbar array structure that includes input lines and output lines interconnected at junctions via electronic devices. The electronic devices of the neuromorphic memory device are programmed to incrementally change states by coupling write signals into the input lines based on: write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device, according to a multiply-accumulate operation, by coupling read signals into one or more of the input lines of the neuromorphic memory device based on: read instructions from the controller and read vectors generated by the interface.

Abstract: A neuromorphic neuron apparatus includes an accumulation block and an output generation block. The apparatus has a current state variable corresponding to previously received one or more signals. The output generation block is configured to use an activation function for generating a current output value based on the current state variable. The accumulation block is configured to repeatedly: compute an adjustment of the current state variable using the current output value and a correction function indicative of a decay behaviour of a time constant of the apparatus; receive a current signal; update the current state variable using the computed adjustment and the received signal, the updated state variable becoming the current state variable; and cause the output generation block to generate a current output value based on the current state variable.

Abstract: The present disclosure relates to a storage device comprising a memory element. The memory element may comprise a changeable physical quantity for storing information. The physical quantity may be in a drifted state. The memory element may be configured for setting the physical quantity to an initial state. Furthermore, the memory element may comprise a drift of the physical quantity from the initial state to the drifted state. The initial state of the physical quantity may be computable by means of an initialization function. The initialization function may be dependent on a target state of the physical quantity and the target state of the physical quantity may be approximately equal to the drifted state of the physical quantity.

Abstract: Training a neural network that comprises nodes and weighted connections between selected ones of the nodes is described herein. A function of a desired activity and a current activity during training results in a feedback signal used for adjusting weight values of the connections. For a weight value update cycle the process determines an importance value for various nodes based on current weight values of the connections and determines an adjustment of the feedback signal specific for each weight value of the connections by a combination of a gradient value derived from the feedback signal for a connection and the determined corresponding element of the adjustment matrix. The updates are applied to the connections during update cycles.

Abstract: The present disclosure relates to an integrated circuit comprising a first neuromorphic neuron apparatus. The first neuromorphic neuron apparatus comprises an input and an accumulation block having a state variable for performing an inference task on the basis of input data comprising a temporal sequence. The first neuromorphic neuron apparatus may be switchable in a first mode and in a second mode. The accumulation block may be configured to perform an adjustment of the state variable using a current input signal of the first neuromorphic neuron apparatus and a decay function indicative of a decay behavior of the apparatus. The state variable may be dependent on previously received one or more input signals of the first neuromorphic neuron apparatus.

Abstract: The present disclosure relates to a storage device comprising a memory element. The memory element may comprise a changeable physical quantity for storing information. The physical quantity may be in a drifted state. The memory element may be configured for setting the physical quantity to an initial state. Furthermore, the memory element may comprise a drift of the physical quantity from the initial state to the drifted state. The initial state of the physical quantity may be computable by means of an initialization function. The initialization function may be dependent on a target state of the physical quantity and the target state of the physical quantity may be approximately equal to the drifted state of the physical quantity.

Abstract: A neural apparatus for a neural network system may be configured to receive one or more input signals during a decode time period, decode the one or more input signals during the decode time period, resulting in a decoded signal, and upon termination of the decode time period, process the decoded signal using internal neuron dynamics. The processed signal may be used to encode and emit one or more output signals in a subsequent decode time period to another neural apparatus of the neural network system.

Abstract: The invention is notably directed to a computer-implemented method for training parameters of a recurrent neural network. The network comprises one or more layers of neuronal units. Each neuronal unit has an internal state, which may also be denoted as unit state. The method comprises providing training data comprising an input signal and an expected output signal to the recurrent neural network. The method further comprises computing, for each neuronal unit, a spatial gradient component and computing, for each neuronal unit, a temporal gradient component. The method further comprises updating the temporal and the spatial gradient component for each neuronal unit at each time instance of the input signal. The computing of the spatial and the gradient component may be performed independently from each other. The invention further concerns a neural network and a related computer program product.

Abstract: Neuromorphic processing apparatus is provided. The present invention may include a spiking neural network comprising a set of input spiking neurons each connected to each of a set of output spiking neurons via a respective synapse for storing a synaptic weight which is adjusted for that synapse in dependence on network operation in a learning mode of the apparatus, and each synapse is operable to provide a post-synaptic signal, dependent on its synaptic weight, to its respective output neuron. The present invention may further include a pre-processor unit adapted to process input data, defining a pattern of data points, to produce a first set of input spike signals which encode values representing respective data points, and a second set of input spike signals which encode values complementary to respective said values representing data points, and to supply the input spike signals to respective predetermined input neurons of the network.

Abstract: The present disclosure relates to a neural network system comprising: a controller including a processing unit configured to execute a spiking neural network, and an interface connecting the controller to an external memory. The controller is configured for executing the spiking neural network, the executing comprising generating read instructions and/or write instructions. The interface is configured for: generating read weighting vectors according to the read instructions, coupling read signals, representing the read weighting vectors, into input lines of the memory, thereby retrieving data from the memory, generating write weighting vectors according to the write instructions, coupling write signals, representing the write weighting vectors, into output lines of the memory, thereby writing data into the memory.

Abstract: Embodiment of the invention are directed to transmitting signals between neurons of a hardware-implemented, spiking neural network (or SNN). The network includes neuronal connections, each including a synaptic unit connecting a pre-synaptic neuron to a post-synaptic neuron. Spikes received from the pre-synaptic neuron of said each neuronal connection are first modulated, in frequency, based on a synaptic weight stored on said each synaptic unit, to generate post-synaptic spikes, such that a first number of spikes received from the pre-synaptic neuron are translated into a second number of post-synaptic spikes. At least some of the spikes received from the pre-synaptic neuron may, each, be translated into a train of two or more post-synaptic spikes. The post-synaptic spikes generated are subsequently transmitted to the post-synaptic neuron of said each neuronal connection. The novel approach makes it possible to obtain a higher dynamic range in the synapse output.

Abstract: In a hardware-implemented approach for operating a neural network system, a neural network system is provided comprising a controller, a memory, and an interface connecting the controller to the memory, where the controller comprises a processing unit configured to execute a neural network and the memory comprises a neuromorphic memory device with a crossbar array structure that includes input lines and output lines interconnected at junctions via electronic devices. The electronic devices of the neuromorphic memory device are programmed to incrementally change states by coupling write signals into the input lines based on: write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device, according to a multiply-accumulate operation, by coupling read signals into one or more of the input lines of the neuromorphic memory device based on: read instructions from the controller and read vectors generated by the interface.

Abstract: A neuromorphic architecture for a spiking neural network comprising a plurality of spiking neurons, each with a plurality of synapses and corresponding synaptic weights, the architecture further comprising a synaptic competition mechanism in connection with a spike-based learning mechanism based on spikes perceived behind a synapse, in which architecture synapses of different neurons connected to the same input compete for that input and based on the result of that competition, each neuron of the neural network develops an individual perception of the presented input spikes, the perception used by the learning mechanism to adjust the synaptic weights.

Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.

Abstract: Neuromorphic methods, systems and devices are provided. The embodiment may include a neuromorphic device which may comprise a crossbar array structure and an analog circuit. The crossbar array structure may include N input lines and M output lines interconnected at junctions via N×M electronic devices, which, in preferred embodiments, include, each, a memristive device. The input lines may comprise N1 first input lines and N2 second input lines. The first input lines may be connected to the M output lines via N1×M first devices of said electronic devices. Similarly, the second input lines may be connected to the M output lines via N2×M second devices of said electronic devices. The analog circuit may be configured to program the electronic devices so as for the first devices to store synaptic weights and the second devices to store neuronal states.

Abstract: A resistive memory cell is connected in circuitry which has a first input terminal for applying neuron input signals including a read portion and a write portion. The circuitry includes a read circuit producing a read signal dependent on resistance of the memory cell, and an output terminal providing a neuron output signal, dependent on the read signal in a first state of the memory cell. The circuitry also includes a storage circuit storing a measurement signal dependent on the read signal, and a switch set operable to supply the read signal to the storage circuit during application of the read portion of each neuron input signal to the memory cell, and, after application of the read portion, to apply the measurement signal in the apparatus to enable resetting of the memory cell to a second state.

Abstract: The present disclosure relates to an apparatus that includes a neuromorphic spike integrator apparatus for neural networks. The apparatus receives at least one input signal encoding information in arrival time of the input signal at the apparatus. The received signal is weighted with a weight value corresponding to the arrival time. The weighted received signal is integrated into a current value of a state of the apparatus and a signal is output based on the current value of the state.