Abstract: A data-processing system with cc-NUMA architecture including a plurality of nodes each constituted by at least one processor intercommunicating with a DRAM-technology local memory using a local bus, the nodes intercommunicating using remote interface bridges and at least one intercommunication ring. The at least one processor has access to a system memory space defined by memory addresses.

Abstract: Interface bridge (13) between a system bus (ASBUS) and at least one local bus (11, 12), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (17, 18, 19) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (20, 21) and capable of addressing the entire system space.

Abstract: In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses into addresses conventionally defined as real, the translation being performed by a first translation unit associated with and managed by the processor which generates the global data. The first translation is followed by the translation of the real address into a physical address generally differing for each local memory and performed by a plurality of translation units, each associated with one of the local memories and managed by the processor associated with that local memory.

Abstract: A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs), where consistency of the global data in each of the local memories is provided by a global write procedure according to which an agent CPUZ, willing to modify a global data in its own local memory, issues a write command on the system bus for performing the write operation in the local memory of another destination CPU of the system and characterizes the write command as a global write, so that all the CPUs connected to the system bus (including CPUZ) detect such command, perform such write operation in their related local memory and provide the destination CPU with a signal indicative of a performed write operation, so that the destination CPU, as "replier", may signal to CPUZ the successful execution of the global write.

Abstract: Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11,12). The priority network directly receives on its input terminals the asynchronous interrupt signals and provides on its output terminals a binary code corresponding to the highest priority interrupt present on its input terminals. The interrupt code is latched in the register and is present on its output terminals. The code latched in the register is used by a validation circuit as a selection code of the related input interrupt signal. If such a signal is present, the code is validated, i.e., it is transferred to the central unit of the system. If the selected interrupt signal is not present, the code is not validated.

Abstract: A microprogrammed control unit with multiple branch capability comprises in addition to a control memory, a first auxiliary read/write memory (21) having low parallelism and a second auxiliary read/write memory (30) having high parallelism. The reading of a microinstruction from the control memory also causes the reading of an information from the first auxiliary memory, such information being used to address the reading of the second auxiliary memory. The information read out from the second auxiliary memory specifies jump conditions (JC1, JC2, JC3) to be examined and jump addresses (JA1, JA2, JA3) and extends the information contained in the microinstruction read out from control memory.Thus it is possible to associate jump (or branch) microinstructions to operative microinstructions and particularly multiple branch microinstructions to curtail the design time of the microprogram and the control memory size devoted to store them.

Abstract: A circuit for coupling together for bidirectional information communication pairs of devices of a digital data processing system, wherein such communication is effected by interlocked information signals, and wherein there is provided a single lead for the bidirectional transfer of such interlocked signals.