Abstract: A processor may boot a system. The processor may determine a type of operation of data based on an application tag. The processor may analyze at least one specific table for the application tag. The processor may perform an operation associated with the application tag.

Abstract: A computer-implemented method, a computer program product, and a computer system for data flow management in a heterogeneous memory device. A media controller redirects traffic from first non-volatile memory (NVM) to second NVM, in response to an instantaneous temperature of the first NVM reaches a first predetermined temperature at which redirecting the traffic is started. The media controller throttles to reduce the traffic to the second NVM, in response to determining that the instantaneous temperature is higher than a second predetermined temperature at which throttling is started. The media controller redirects the traffic back to the first NVM, in response to determining that the instantaneous temperature is not higher than the second predetermined temperature and lower than a third predetermined temperature at which throttling is ended. The first NVM is thermally sensitive, while the second NVM is thermally tolerant.

Abstract: Configuration and dynamic profiling of storage class memory (SCM) devices is provided. Information is retrieved that includes historical SCM device configurations, historical SCM device utilization, functional and non-functional properties of a plurality of SCM devices on a host node, current real time utilization of the plurality of SCM devices by an application workload of a customer running on the host node, and relationships between the plurality of SCM devices, needs of the customer, and resource capabilities and real time resource utilization on the host node. A configuration of each respective SCM device is determined based on retrieved information and an artificial intelligence-predicted SCM device future utilization trajectory of the customer. Each respective SCM device is dynamically configured with a set of SCM device partitions according to a corresponding SCM device profile based on the determined configuration of each respective SCM device of the plurality of SCM devices.

Abstract: A processor may boot a system. The processor may determine a type of operation of data based on an application tag. The processor may analyze at least one specific table for the application tag. The processor may perform an operation associated with the application tag.

Abstract: In an example, a computer system includes: a hardware platform including a processor, system memory, and a plurality of input/output (IO) devices, the processor including a controller having a trace and optimize function controller (TOF); and a software platform including an operating system (OS) executing on the hardware platform; wherein the TOF is configured to communicate with the processor, the system memory, and the plurality of IO devices to obtain current settings thereof and to determine final settings for the processor, the system memory, and the plurality of IO devices based on the current settings; and wherein the controller is configured to control the processor, the system memory, and the plurality of IO devices based on the final settings.

Abstract: Aspects of the present invention disclose a method, computer program product, and system for implementing wear leveling across a drive array. The method includes one or more processors identifying a set of storage devices in a storage system. Each storage device of the set of storage devices assigned to a corresponding endurance tier based on historical utilization. The endurance tiers correspond to a range of device endurance remaining for a storage device. The method further includes one or more processors monitoring real-time endurance factor information for the set of storage devices. In response to determining that the monitored real-time endurance factor information indicates that the set of storage devices are not wearing evenly, the method further includes one or more processors reassigning at least one storage device of the set of storage devices to an updated endurance tier, corresponding to utilization of the at least one storage device.

Abstract: Embodiments of the present invention include detecting one or more memory modules coupled to a memory controller via a memory channel. A total power requirement for the one or more memory modules is determined. A voltage regulator module set point of the memory channel is adjusted based at least in part on the power requirement for the one or more memory modules. The voltage regulator module provides power to the memory modules and is characterized by an optimal load current value where the voltage regulator module operates at a peak efficiency. An operating mode of the memory controller is determined. Based on determining that the memory controller is operating in a first mode, the commands serviced by the one or more memory modules are throttled by the memory controller to keep a load current of the memory channel within a range of the optimal load current value.

Abstract: In an example, a computer system includes: a hardware platform including a processor, system memory, and a plurality of input/output (IO) devices, the processor including a controller having a trace and optimize function controller (TOF); and a software platform including an operating system (OS) executing on the hardware platform; wherein the TOF is configured to communicate with the processor, the system memory, and the plurality of IO devices to obtain current settings thereof and to determine final settings for the processor, the system memory, and the plurality of IO devices based on the current settings; and wherein the controller is configured to control the processor, the system memory, and the plurality of IO devices based on the final settings.

Abstract: Embodiments of the present invention include detecting one or more memory modules coupled to a memory controller via a memory channel. A total power requirement for the one or more memory modules is determined. A voltage regulator module set point of the memory channel is adjusted based at least in part on the power requirement for the one or more memory modules. The voltage regulator module provides power to the memory modules and is characterized by an optimal load current value where the voltage regulator module operates at a peak efficiency. An operating mode of the memory controller is determined. Based on determining that the memory controller is operating in a first mode, the commands serviced by the one or more memory modules are throttled by the memory controller to keep a load current of the memory channel within a range of the optimal load current value.

Abstract: Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal.

Abstract: A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file.

Abstract: Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal.

Abstract: A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file.