Patents by Inventor Anil KAVALA
Anil KAVALA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230091026Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.Type: ApplicationFiled: November 26, 2022Publication date: March 23, 2023Inventors: Anil Kavala, Seonkyoo Lee, Taesung Lee, Jeongdon Ihm, Byunghoon Jeong
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Patent number: 11522550Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.Type: GrantFiled: October 22, 2020Date of Patent: December 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Anil Kavala, Seonkyoo Lee, Taesung Lee, Jeongdon Ihm, Byunghoon Jeong
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Patent number: 11367471Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.Type: GrantFiled: June 21, 2021Date of Patent: June 21, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Anil Kavala, Tongsung Kim, Chiweon Yoon, Byunghoon Jeong
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Publication number: 20220148630Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.Type: ApplicationFiled: June 21, 2021Publication date: May 12, 2022Inventors: Anil Kavala, Tongsung Kim, Chiweon Yoon, Byunghoon Jeong
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Publication number: 20210320664Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.Type: ApplicationFiled: October 22, 2020Publication date: October 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Anil Kavala, Seonkyoo Lee, Taesung Lee, Jeongdon Ihm, Byunghoon Jeong
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Semiconductor memory device, semiconductor memory module, and method of accessing nonvolatile memory
Patent number: 10777269Abstract: A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.Type: GrantFiled: March 12, 2019Date of Patent: September 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jiwan Jung, Anil Kavala, Taesung Lee, Jeongdon Ihm -
SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY MODULE, AND METHOD OF ACCESSING NONVOLATILE MEMORY
Publication number: 20200066336Abstract: A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.Type: ApplicationFiled: March 12, 2019Publication date: February 27, 2020Inventors: JIWAN JUNG, ANIL KAVALA, TAESUNG LEE, JEONGDON IHM -
Patent number: 10439632Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.Type: GrantFiled: November 14, 2018Date of Patent: October 8, 2019Assignee: SAMSING ELECTRONICS CO., LTD.Inventors: Anil Kavala, Seon-kyoo Lee, Byung-hoon Jeong, Jeong-don Ihm, Young-don Choi
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Publication number: 20190158109Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.Type: ApplicationFiled: November 14, 2018Publication date: May 23, 2019Inventors: Anil KAVALA, Seon-kyoo LEE, Byung-hoon JEONG, Jeong-don IHM, Young-don CHOI
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Patent number: 10171269Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.Type: GrantFiled: April 15, 2016Date of Patent: January 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon-Kyoo Lee, Jeong-Don Ihm, Anil Kavala, Byung-Hoon Jeong
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Publication number: 20170048087Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.Type: ApplicationFiled: April 15, 2016Publication date: February 16, 2017Inventors: SEON-KYOO LEE, Jeong-Don IHM, Anil KAVALA, Byung-Hoon JEONG