Patents by Inventor Anilkumar Mandapuram
Anilkumar Mandapuram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10042758Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.Type: GrantFiled: April 16, 2015Date of Patent: August 7, 2018Assignee: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
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Patent number: 10037272Abstract: A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.Type: GrantFiled: March 15, 2013Date of Patent: July 31, 2018Assignee: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
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Patent number: 9824050Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.Type: GrantFiled: November 20, 2015Date of Patent: November 21, 2017Assignee: Avalanche Technology, Inc.Inventors: Anilkumar Mandapuram, Siamack Nemazie
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Publication number: 20160085705Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.Type: ApplicationFiled: November 20, 2015Publication date: March 24, 2016Inventors: Anilkumar Mandapuram, Siamack Nemazie
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Patent number: 9251059Abstract: A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided.Type: GrantFiled: April 8, 2013Date of Patent: February 2, 2016Assignee: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Ngon Van Le, Anilkumar Mandapuram
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Patent number: 9229892Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.Type: GrantFiled: April 15, 2014Date of Patent: January 5, 2016Assignee: AVALANCHE TECHNOLOGY, INC.Inventors: Anilkumar Mandapuram, Siamack Nemazie
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Patent number: 9158623Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.Type: GrantFiled: November 11, 2014Date of Patent: October 13, 2015Assignee: AVALANCHE TECHNOLOGY, INC.Inventors: Siamack Nemazie, Anilkumar Mandapuram
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Publication number: 20150220435Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
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Patent number: 9037786Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.Type: GrantFiled: August 19, 2013Date of Patent: May 19, 2015Assignee: AVALANCHE TECHNOLOGY, INC.Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
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Publication number: 20150067449Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.Type: ApplicationFiled: November 11, 2014Publication date: March 5, 2015Inventors: Siamack Nemazie, Anilkumar Mandapuram
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Patent number: 8935599Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.Type: GrantFiled: February 13, 2014Date of Patent: January 13, 2015Assignee: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Anilkumar Mandapuram
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Publication number: 20140281069Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.Type: ApplicationFiled: April 15, 2014Publication date: September 18, 2014Applicant: Avalanche Technology, Inc.Inventors: Anilkumar Mandapuram, Siamack Nemazie
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Publication number: 20140281825Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.Type: ApplicationFiled: February 13, 2014Publication date: September 18, 2014Applicant: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Anilkumar Mandapuram
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Publication number: 20140281142Abstract: A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided.Type: ApplicationFiled: April 8, 2013Publication date: September 18, 2014Applicant: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Ngon Van Le, Anilkumar Mandapuram
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Patent number: 8806098Abstract: A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.Type: GrantFiled: April 3, 2013Date of Patent: August 12, 2014Assignee: Avalanche Technology, Inc.Inventors: Anilkumar Mandapuram, Siamack Nemazie
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Patent number: 8656255Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.Type: GrantFiled: March 15, 2013Date of Patent: February 18, 2014Assignee: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Anilkumar Mandapuram
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Publication number: 20140047166Abstract: A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.Type: ApplicationFiled: March 15, 2013Publication date: February 13, 2014Applicant: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
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Publication number: 20130339587Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.Type: ApplicationFiled: August 19, 2013Publication date: December 19, 2013Applicant: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram