Abstract: Photoresponse from a ferroelectric optical computing device, such as a memory cell or a logic switch, is increased by either illuminating the regions of the ferroelectric crystal under the electrode edges in a sandwich structure device or by aligning the principal axis of the ferroelectric crystal parallel to the linear polarization vector of the optical beam. Device density is increased by reducing the beam size using a small near-field optical fiber. Device evaluation including imprint failure susceptibility is performed by illuminating each ferroelectric optical computing device in a large array of such devices and storing the device address of any device whose response departs from a normal range.

Abstract: Photoresponse from a ferroelectric optical computing device, such as a memory cell or a logic switch, is increased by either illuminating the regions of the ferroelectric crystal under the electrode edges in a sandwich structure device or by aligning the principal axis of the ferroelectric crystal parallel to the linear polarization vector of the optical beam. Device density is increased by reducing the beam size using a small near-field optical fiber. Device evaluation including imprint failure susceptibility is performed by illuminating each ferroelectric optical computing device in a large array of such devices and storing the device address of any device whose response departs from a normal range.

Abstract: Photoresponse from a ferroelectric optical computing device, such as a memory cell or a logic switch, is increased by either illuminating the regions of the ferroelectric crystal under the electrode edges in a sandwich structure device or by aligning the principal axis of the ferroelectric crystal parallel to the linear polarization vector of the optical beam. Device density is increased by reducing the beam size using a small near-field optical fiber. Device evaluation including imprint failure susceptibility is performed by illuminating each ferroelectric optical computing device in a large array of such devices and storing the device address of any device whose response departs from a normal range.

Abstract: High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

Abstract: This invention is a novel high-speed neural network based processor for solving the "traveling salesman" and other global optimization problems. It comprises a novel hybrid architecture employing a binary synaptic array whose embodiment incorporates the fixed rules of the problem, such as the number of cities to be visited. The array is prompted by analog voltages representing variables such as distances. The processor incorporates two interconnected feedback networks, each of which solves part of the problem independently and simultaneously, yet which exchange information dynamically.

Abstract: An electrically programmable, optically readable data or memory cell is configured from a thin film of ferroelectric material, such as PZT, sandwiched between a transparent top electrode and a bottom electrode. The output photoresponse, which may be a photocurrent or photo-emf, is a function of the product of the remanent polarization from a previously applied polarization voltage and the incident light intensity. The cell is useful for analog and digital data storage as well as opto-electric computing. The optical read operation is non-destructive of the remanent polarization. The cell provides a method for computing the product of stored data and incident optical data by applying an electrical signal to store data by polarizing the thin film ferroelectric material, and then applying an intensity modulated optical signal incident onto the thin film material to generate a photoresponse therein related to the product of the electrical and optical signals.

Abstract: An electrically programmable, erasable, read-only memory is comprised of an array of vertical porous floating gate MOSFET structures in a layer of a-Si with parallel X and parallel Y conductors on opposite sides of the a-Si layer functioning as source and drain electrodes. The floating gate of each vertical MOSFET structure consists of a plurality of electrically insulated metallic particles embedded in the a-Si layer between said source and said drain electrodes with the metallic particles adjacent to the source electrodes. The insulation between the metallic particles and the a-Si material is thick enough to prevent tunneling of electrons but the insulation between the particles and the source electrode is thinner to allow tunneling of electrons at a predetermined threshold voltage to store a charge in the porous floating gate. Alternatively, the metal particles may be gathered into one insulated toroidal gate which controls current through a-Si in the center of the toroidal gate.

Abstract: MnO.sub.2-x thin films (12) exhibit irreversible memory switching (28) with an "OFF/ON" resistance ratio of at least about 10.sup.3 and the tailorability of "ON" state (20) resistance. Such films are potentially extremely useful as a "connection" element in a variety of microelectronic circuits and arrays (24). Such films provide a pre-tailored, finite, non-volatile resistive element at a desired place in an electric circuit, which can be electrically turned OFF (22) or "disconnected" as desired, by application of an electrical pulse. Microswitch structures (10) constitute the thin film element, contacted by a pair of separate electrodes (16a, 16b) and have a finite, pre-selected ON resistance which is ideally suited, for example, as a programmable binary synaptic connection for electronic implementation of neural network architectures. The MnO.sub.

Abstract: Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

Abstract: A multi-layered, thin-film, digital memory having associative recall. There is a first memory matrix and a second memory matrix.

Abstract: Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Abstract: Thin films of niobium nitride with high superconducting temperature (T.sub.c) of 15.7.degree. K. are deposited on substrates held at room temperature (.about.90.degree. C.) by heat sink throughout the sputtering process. Films deposited at P.sub.Ar >12.9.+-.0.2 mTorr exhibit higher T.sub.c with increasing P.sub.N2,I, with the highest T.sub.c achieved at P.sub.N2,I =3.7.+-.0.2 mTorr and total sputtering pressure P.sub.tot =16.6.+-.0.4. Further increase of N.sub.2 injection starts decreasing T.sub.c.

Abstract: Disclosed is a method of coating a substrate with an amorphous metal comprising the step of bombarding a solid piece of the metal with ions of an inert gas in the presence of a magnetic field to provide a vapor of the metal which is deposited on the substrate at a sufficiently low gas pressure so that there is formed on the substrate a thin, uniformly thick, essentially pinhole-free film of the metal.