Abstract: Embodiments are disclosed for expanding a seed scene using proposals from a generative model of scene graphs. The method may include clustering subgraphs according to respective one or more maximal connected subgraphs of a scene graph. The scene graph includes a plurality of nodes and edges. The method also includes generating a scene sequence for the scene graph based on the clustered subgraphs. A first machine learning model determines a predicted node in response to receiving the scene sequence. A second machine learning model determines a predicted edge in response to receiving the scene sequence and the predicted node. A scene graph is output according to the predicted node and the predicted edge.

Abstract: Methods, systems, and robots for multi-layer prepreg composite sheet layup. The robotic system may include a memory for storing a dataset including start and end point pairs of a mold of a 3D part that defines a layup sequence, a first robot or a first robot arm that is configured to conform a prepreg layer or sheet onto the mold of the 3D part, and a second robot or a second robot arm that is configured to hold or grasp the prepreg layer or sheet above the mold of the 3D part and stretch or relax the prepreg layer or sheet when the first robot or the first robot arm conforms the prepreg layer or sheet onto the mold. The robotic system may also include one or more processors connected to the first robot or the first robot arm and the second robot or the second robot arm.

Abstract: A system and method for real-life interactive experience between virtual participants in a gathering of up to thousands of people attending a streamed event, using their computers and mobile devices. The virtual participants sit at boxes and tables at the event and see video and hear audio of other participants sitting at the same table and box. The participants interact with other participants of their choosing without disturbing the rest of the participants. They can use local chat boxes and global chat boxes to chat with the participants of the event. The participants may virtually move from one area to another area of the event using the event layout and sit in a new area of their choosing as they would at an in-person event while watching the streaming of the event thus providing a close to real-life experience of interacting with the event participants.

Abstract: An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

Abstract: An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.

Abstract: An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.