Abstract: An internal matrix corresponding to a representation of a display screen and having transparency data of a macro block is accessed. Display plane data from either a first or second plane is read if the internal matrix indicates the macro block is non-translucent and from both planes when the internal matrix indicates translucency. A high-level external matrix having high-level external transparency data indicating transparency of pixels is accessed if the internal transparency data indicates the macro block includes a window boundary. Display plane data from either the first or second plane is read if the high-level external transparency data indicates a non-translucent pixel and from both planes when the internal matrix indicates translucency. A detailed external matrix is accessed if the internal transparency data indicates the macro block is translucent or if the high-level external transparency data indicates the pixel is translucent. The first and second planes are blended accordingly.

Abstract: Systems and methods for hardware-accelerated key color extraction are disclosed. An update corresponding to a portion of a digital representation of a display screen is received. Key color information for locations within the update is identified. A data structure code associated with the portion of the digital representation of the display screen is determined based on the identification of the key color information. The data structure code is provided to a data structure. During a scan of the frame buffer for display, the frame buffer is capable of being read according to the data structure.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. However, the video output system must often compete with other memory users in order to access a frame buffer in a shared memory system. When memory bandwidth resources are limited, the performance of a computer system will suffer. To reduce the performance drop, a dynamic color mode switching system has been introduced. The dynamic color mode switching system detects when memory bandwidth resources are limited and then instructs the video output system to switch to a color mode that reduces the amount of reads from the memory system without any user intervention.

Abstract: Systems and methods for compositing an image from display planes are disclosed. An internal matrix having transparency data indicating transparency of a macro block of a digital representation of a display is accessed. An external matrix is accessed if the internal matrix indicates the macro block includes a transparent and opaque pixel, wherein the external matrix has transparency data indicating transparency of each pixel in the macro block. A first display plane is read based on the transparency data indicating opaque pixels and the first display plane data is sent to a first buffer. Second display plane data of a second display plane is read and sent to a second buffer if the transparency data indicates transparent pixels. Control data is inserted into the first buffer accordingly such that an image is generated based on at least one of the first and second display plane data and the control data.

Abstract: An internal matrix corresponding to a representation of a display screen and having transparency data of a macro block is accessed. Display plane data from either a first or second plane is read if the internal matrix indicates the macro block is non-translucent and from both planes when the internal matrix indicates translucency. A high-level external matrix having high-level external transparency data indicating transparency of pixels is accessed if the internal transparency data indicates the macro block includes a window boundary. Display plane data from either the first or second plane is read if the high-level external transparency data indicates a non-translucent pixel and from both planes when the internal matrix indicates translucency. A detailed external matrix is accessed if the internal transparency data indicates the macro block is translucent or if the high-level external transparency data indicates the pixel is translucent. The first and second planes are blended accordingly.

Abstract: Systems and methods for compositing an image from display planes are disclosed. An internal matrix having transparency data indicating transparency of a macro block of a digital representation of a display is accessed. An external matrix is accessed if the internal matrix indicates the macro block includes a transparent and opaque pixel, wherein the external matrix has transparency data indicating transparency of each pixel in the macro block. A first display plane is read based on the transparency data indicating opaque pixels and the first display plane data is sent to a first buffer. Second display plane data of a second display plane is read and sent to a second buffer if the transparency data indicates transparent pixels. Control data is inserted into the first buffer accordingly such that an image is generated based on at least one of the first and second display plane data and the control data.

Abstract: Systems and methods for hardware-accelerated key color extraction are disclosed. An update corresponding to a portion of a digital representation of a display screen is received. Key color information for locations within the update is identified. A data structure code associated with the portion of the digital representation of the display screen is determined based on the identification of the key color information. The data structure code is provided to a data structure. During a scan of the frame buffer for display, the frame buffer is capable of being read according to the data structure.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, full-motion video may also be displayed in a window defined in the frame buffer. If the native resolution of the full-motion video is larger than the window defined in said frame buffer then valuable memory space and memory bandwidth is being wasted by writing said larger full-motion video in a memory system (and later reading it back) when some data from the full-motion video will be discarded. Thus, a video pre-processor is disclosed to reduce the size of the full-motion video before that full-motion video is written into a memory system. The video pre-processor will scale the full-motion video down to a size no larger than the window defined in the frame buffer.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: Systems and methods for an efficient display data transfer algorithm over a network are disclosed. A compressed frame buffer update transmitted from a server via a network is received by a hardware decompression engine. The hardware decompression engine identifies one or more palette entries indicated in the compressed frame buffer update and determines whether the one or more palette entries is stored in a palette cache of the hardware decompression engine. If the one or more palette entries is not stored in the palette cache, the hardware decompression engine writes the one or more palette entries from an external palette memory to the palette cache. Decompressed display data is generated based on the compressed frame buffer update using the palette cache. The decompressed display data is written to an output buffer of the hardware decompression engine.

Abstract: Systems and methods for an efficient display data transfer algorithm over a network are disclosed. A compressed frame buffer update transmitted from a server via a network is received by a hardware decompression engine. The hardware decompression engine identifies one or more palette entries indicated in the compressed frame buffer update and determines whether the one or more palette entries is stored in a palette cache of the hardware decompression engine. If the one or more palette entries is not stored in the palette cache, the hardware decompression engine writes the one or more palette entries from an external palette memory to the palette cache. Decompressed display data is generated based on the compressed frame buffer update using the palette cache. The decompressed display data is written to an output buffer of the hardware decompression engine.

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. However, the video output system must often compete with other memory users in order to access a frame buffer in a shared memory system. When memory bandwidth resources are limited, the performance of a computer system will suffer. To reduce the performance drop, a dynamic color mode switching system has been introduced. The dynamic color mode switching system detects when memory bandwidth resources are limited and then instructs the video output system to switch to a color mode that reduces the amount of reads from the memory system without any user intervention.

Abstract: A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, full-motion video may also be displayed in a window defined in the frame buffer. If the native resolution of the full-motion video is larger than the window defined in said frame buffer then valuable memory space and memory bandwidth is being wasted by writing said larger full-motion video in a memory system (and later reading it back) when some data from the full-motion video will be discarded. Thus, a video pre-processor is disclosed to reduce the size of the full-motion video before that full-motion video is written into a memory system. The video pre-processor will scale the full-motion video down to a size no larger than the window defined in the frame buffer.

Abstract: In a digital video processing system for processing full-motion video in computer terminal systems, two main rendering paths are created for a computer terminal system: a screen buffer path and a full-motion video path. The screen buffer path renders a desktop display from a screen buffer within the terminal system. The full-motion video path decodes a video stream and then processes the decoded video stream with a video processing pipeline to fit the video frames within a destination video window within the desktop display. The video processing pipeline performs clipping, blending, chroma resampling, resizing, and color converting of the video frames in pipelined stages with minimal memory accesses. A video adapter then combines the desktop display with the processed digital video for a final terminal display.

Abstract: An input detector detects the bit rate and signal type of multiple signals at corresponding multiple interface ports. A master controller coupled to the detector sends control signals to different types of framers such that signals received at one of the multiple interface ports is operated on by a framer corresponding to the signals format type. In addition, an Ethernet aggregator may combine multiple Ethernet frames of different sizes into a single frame so when it is mapped into a SONET frame, essentially all of the SONET frame is used. A SONET mapper generates and inserts information into a frame that identifies the contents of the information contained therein. At a receiving end, the mapper can determine from this information the contents, and can instruct a controller which framer/unframer to send the frame information to.