Abstract: A memory (10) that has a shorter access time and higher reliability in a special mode of operation. In one form, the memory (10) has a special mode of operation in which multiple memory rows are simultaneously selected. As a consequence, multiple memory cells (44) are used to drive each bit line pair. Using multiple memory cells (44) to drive each bit line pair allows the bit lines to be driven to the proper logic state in a shorter time. This speeds up accesses to memory (10). Using multiple memory cells (44) to drive each bit line pair also improves the reliability of memory (10). Because multiple memory cells (44) are used to drive the same bit line pair, a failure of one memory cell (44) still leaves one or more functioning memory cells (44) to drive the correct logic state on the bit line pair. The memory may be incorporated in a cache controller of a data processing system in which only a part of the memory is being used.

Abstract: In accordance with the present invention, a resource allocation array has at least one resource input line (Aj), at least one request for resource input line (Ri) and at least one cell (12) coupled to the at least one resource input line and to the at least one request for resource line. The resource allocation array assigns one resource to one request for the resource. The one resource and the one request for the resource are both of a group of at least one resource and of a group of at least one request for the resource, respectively. The availability and unavailability of the resource is represented by a first and a second predetermined resource signal, respectively. The assertion and non assertion of the request for resource is represented by a third and a fourth predetermined request for resource signal, respectively. The at least one resource input line is associated with one of the at least one resource signals.

Abstract: A latching sense amplifier (10) has sensing circuitry (12 and 14), latching circuitry (16) and switching circuitry (18). The sense amplifier operates between a first and a second voltage supply level and receives two input voltage levels. In a first mode, the sensing circuitry (12 and 14) generates two AC symmetric outputs representative of the voltage differential between the two input voltages. In a second mode, the latching circuitry (16) receives the two AC symmetric outputs and generates a second pair of outputs. The second pair of outputs is also representative of the voltage differential between the two input voltages. The voltage differential between the second pair of outputs is generally equal to the voltage differential between the first and second voltage supply levels. The switching circuitry (18) configures the sensing circuitry (12 and 14) to operate in conjunction with the latching circuitry (16) to form a cross coupled latch in the second mode.