Abstract: A circuit system includes a processing integrated circuit die comprising a first die-to-die interface circuit and a memory interface circuit. The circuit system also includes a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die. The first and the second die-to-die interface circuits are coupled together. The compute circuit is coupled to exchange information with the memory interface circuit through the first and the second die-to-die interface circuits.

Abstract: Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.

Abstract: An integrated circuit includes logic circuits, first buffer circuits coupled to external ports of the integrated circuit, second buffer circuits that are each coupled to one of the logic circuits, and a crossbar circuit coupled to the first and the second buffer circuits. The crossbar circuit is configurable to provide data transfer between the logic circuits and the external ports of the integrated circuit through the first buffer circuits and the second buffer circuits.

Abstract: This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.

Abstract: A circuit system includes an accelerator circuit and a compute circuit. The accelerator circuit generates a request in response to receiving packets of data. The accelerator circuit generates an indication of a low power state based on a reduced number of the packets of data being received. The compute circuit performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request. The compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the low power state from the accelerator circuit.

Abstract: Systems and methods are provided for a modular die-to-die interconnect for integrated circuits in a three-dimensional arrangement. An integrated circuit system may include a first chiplet that includes a grid-based interconnect field and a second chiplet that includes a complementary grid-based interconnect field. A number of interconnects of the complementary grid-based interconnect field of the second chiplet are connected to a corresponding number of interconnects of the grid-based interconnect field of the first chiplet.

Abstract: A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including one or more power monitors and one or more thermal sensors. The programmable logic device may include control circuitry that may receive power data and thermal data for multiple die of the programmable logic device, and may implement one or more response based on the thermal and power data.

Abstract: Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.

Abstract: A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Abstract: A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that generates a gating signal based on the clock signal and an enable signal. The clock gating circuit also includes a logic gate that generates a control signal based on the gating signal. The clock gating circuit also includes gated clock generation circuitry that generates a gated clock signal based on the clock signal and the control signal.

Abstract: A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

Abstract: Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or power model of the programmable logic device that operates at a voltage level that is not other than a predefined voltage defined by a voltage library. A system of the present disclosure may interpolate between voltage levels defined by the voltage libraries to generate a new voltage library for the programmable logic device. A timing and/or power model may be generated for the programmable logic device based on the new voltage library and the programmable logic device may be analyzed using the timing and/or power model at the interpolated voltage. The timing and/or power model may be used to generate a bitstream that is used to program the integrated circuit.

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Abstract: Systems or methods of the present disclosure may provide for operating a programmable fabric including multiple programmable elements organized into a number of power domains that utilize a common voltage within the respective power domains. A current sensor senses a current of the programmable fabric. When the sensed current has crossed a threshold, the programmable fabric changes the number of power domains.

Abstract: Systems or methods of the present disclosure may provide for determining a loadline for operation of a programmable logic fabric where the loadline is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The loadline may be determined using software modeling for the design or configuration. Additionally or alternatively, the loadline may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.